AD9122 Analog Devices, AD9122 Datasheet - Page 33

• Manufacturer Part Number: AD9122
• Manufacturer: Analog Devices

Specifications of AD9122

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

The setup (t
are shown in Figure 46. The minimum setup and hold times
are shown in Table 13.
Table 13. Data to DCI Setup and Hold Times
DCI Delay
Register 0x16,
Bits[1:0]
00
01
10
11
The data interface timing can be verified by using the sample
error detection (SED) circuitry. See the Interface Timing
Validation section for more information.
DATA
DCI
S
) and hold (t
Figure 46. Timing Diagram for Input Data Port
t
Minimum Setup
Time, t
−0.05
−0.23
−0.38
−0.47
S
SAMPLING
INTERVAL
t
H
t
DATA
S
(ns)
FIFO SOFT ALIGN REQUEST
H
) times, with respect to the edges,
FRAME
DATA
DCI
Minimum Hold
Time, t
0.65
0.95
1.22
1.38
t
S
LATCH
INPUT
REG 0x18[1]
SAMPLING
INTERVAL
t
DATA
t
H
H
(ns)
FORMAT
DATA
Sampling
Interval (ns)
0.6
0.72
0.84
0.91
DATA/FIFO RATE
Figure 47. Block Diagram of FIFO
32
POINTER
REG 0x10[6]
WRITE
Rev. B | Page 33 of 60
32 BITS
RESET
REG 0
REG 1
REG 2
REG 3
REG 4
REG 5
REG 6
REG 7
LOGIC
FIFO PHASE OFFSET
REG 0x17[2:0]
FIFO OPERATION
The AD9122 contains a 2-channel, 16-bit wide, eight-word deep
FIFO designed to relax the timing relationship between the data
arriving at the DAC input ports and the internal DAC data rate
clock. The FIFO acts as a buffer that absorbs timing variations
between the data source and the DAC, such as the clock-to-data
variation of an FPGA or ASIC, which significantly increases the
timing budget of the interface.
Figure 47 shows the block diagram of the datapath through
the FIFO. The data is latched into the device, is formatted, and
is then written into the FIFO register determined by the FIFO
write pointer. The value of the write pointer is incremented
every time a new word is loaded into the FIFO. Meanwhile, data
is read from the FIFO register determined by the read pointer
and fed into the digital datapath. The value of the read pointer
is incremented every time data is read into the datapath from
the FIFO. The FIFO pointers are incremented at the data rate
(DACCLK rate divided by the interpolation ratio).
Valid data is transmitted through the FIFO as long as the FIFO
does not overflow or become empty. An overflow or empty
condition of the FIFO occurs when the write pointer and read
pointer point to the same FIFO location. This simultaneous
access of data leads to unreliable data transfer through the FIFO
and must be avoided.
Nominally, data is written to and read from the FIFO at the same
rate. This keeps the FIFO depth constant. If data is written to
the FIFO faster than data is read out, the FIFO depth increases.
If data is read out of the FIFO faster than data is written to it,
the FIFO depth decreases. For optimum timing margin, the
FIFO depth should be maintained near half full (a difference of
4 between the write pointer and read pointer values). The FIFO
depth represents the FIFO pipeline delay and is part of the over-
all latency of the AD9122.
POINTER
READ
32
I AND Q
PATHS
DATA
÷ INT
32
I AND Q
DACS
DACCLK
SYNC
AD9122