AD9122 Analog Devices, AD9122 Datasheet - Page 6

• Manufacturer Part Number: AD9122
• Manufacturer: Analog Devices

Specifications of AD9122

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9122
DIGITAL SPECIFICATIONS
T
noted.
Table 2.
Parameter
CMOS INPUT LOGIC LEVEL
CMOS OUTPUT LOGIC LEVEL
LVDS RECEIVER INPUTS
DAC CLOCK INPUT (DACCLKP, DACCLKN)
REFCLK INPUT (REFCLKP, REFCLKN)
SERIAL PORT INTERFACE
1
DIGITAL INPUT DATA TIMING SPECIFICATIONS
Table 3.
Parameter
LATENCY (DACCLK CYCLES)
LVDS receiver is compliant with the IEEE 1596 reduced range link, unless otherwise noted.
MIN
Input V
Input V
Output V
Output V
Input Voltage Range, V
Input Differential Threshold, V
Input Differential Hysteresis, V
Receiver Differential Input Impedance, R
LVDS Input Rate
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Maximum Clock Rate
Differential Peak-to-Peak Voltage
Common-Mode Voltage
REFCLK Frequency (PLL Mode)
REFCLK Frequency (SYNC Mode)
Maximum Clock Rate (SCLK)
Minimum Pulse Width High (t
Minimum Pulse Width Low (t
Setup Time, SDIO to SCLK (t
Hold Time, SDIO to SCLK (t
Data Valid, SDO to SCLK (t
Setup Time, CS to SCLK (t
1× Interpolation (With or Without Modulation)
2× Interpolation (With or Without Modulation)
4× Interpolation (With or Without Modulation)
8× Interpolation (With or Without Modulation)
Inverse Sinc
Fine Modulation
to T
MAX
IN
IN
Logic High
Logic Low
OUT
OUT
, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I
Logic High
Logic Low
1
IA
or V
DCSB
DV
DH
DS
)
IB
)
)
PWL
)
PWH
IDTH
IDTHH
)
)
to V
IDTHL
IN
Test Conditions/Comments
IOVDD = 1.8 V
IOVDD = 2.5 V
IOVDD = 3.3 V
IOVDD = 1.8 V
IOVDD = 2.5 V, 3.3 V
IOVDD = 1.8 V
IOVDD = 2.5 V
IOVDD = 3.3 V
IOVDD = 1.8 V, 2.5 V, 3.3 V
Applies to data, DCI, and FRAME inputs
See Table 5
Self-biased input, ac-coupled
1 GHz ≤ f
See the Multichip Synchronization section
for conditions
Value
64
135
292
608
20
8
VCO
Rev. B | Page 6 of 60
≤ 2.1 GHz
Unit
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
FS
= 20 mA, maximum sample rate, unless otherwise
1.2
1.6
2.0
1.4
Min
1.8
2.4
825
−100
80
100
1230
100
15.625
0
40
1.9
0.2
2.3
Typ
20
500
1.25
500
1.25
1.4
Max
0.6
0.8
0.4
1675
+100
120
2000
2000
600
600
12.5
12.5
Unit
V
V
V
V
V
V
V
V
V
mV
mV
mV
Ω
mV
V
MHz
mV
V
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns