AD9122 Analog Devices, AD9122 Datasheet - Page 43

• Manufacturer Part Number: AD9122
• Manufacturer: Analog Devices

Specifications of AD9122

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

QUADRATURE PHASE CORRECTION
The purpose of the quadrature phase correction block is to
enable compensation of the phase imbalance of the analog
quadrature modulator following the DAC. If the quadrature
modulator has a phase imbalance, the unwanted sideband
appears with significant energy. Tuning the quadrature phase
adjust value can optimize image rejection in single sideband
radios.
Ordinarily, the I and Q channels have an angle of precisely 90°
between them. The quadrature phase adjustment is used to change
the angle between the I and Q channels. When I Phase Adj[9:0]
(Register 0x38 and Register 0x39) is set to 1000000000, the I DAC
output moves approximately 1.75° away from the Q DAC output,
creating an angle of 91.75° between the channels. When I Phase
Adj[9:0] is set to 0111111111, the I DAC output moves approx-
imately 1.75° toward the Q DAC output, creating an angle of
88.25° between the channels.
Q Phase Adj[9:0] (Register 0x3A and Register 0x3B) works in
a similar fashion. When Q Phase Adj[9:0] is set to 1000000000,
the Q DAC output moves approximately 1.75° away from the
I DAC output, creating an angle of 91.75° between the channels.
When Q Phase Adj[9:0] is set to 0111111111, the Q DAC output
moves approximately 1.75° toward the I DAC output, creating
an angle of 88.25° between the channels.
Based on these two endpoints, the combined resolution of the
phase compensation register is approximately 3.5°/1024 or
0.00342° per code.
DC OFFSET CORRECTION
The dc value of the I datapath and the Q datapath can be
independently controlled by adjusting the I DAC Offset[15:0]
and Q DAC Offset[15:0] values in Register 0x3C through
Register 0x3F. These values are added directly to the datapath
values. Care should be taken not to overrange the transmitted
values.
Figure 61 shows how the DAC offset current varies as a function
of the I DAC Offset[15:0] and Q DAC Offset[15:0] values. With
the digital inputs fixed at midscale (0x0000, twos complement data
format), Figure 61 shows the nominal I
as the DAC offset value is swept from 0 to 65,535. Because I
and I
and I
OUTxN
OUTxN
are complementary current outputs, the sum of I
is always 20 mA.
OUTxP
and I
OUTxN
currents
OUTxP
OUTxP
Rev. B | Page 43 of 60
INVERSE SINC FILTER
The inverse sinc (sinc
response of the sinc
is shown in Figure 62. The composite response has a pass-band
ripple of less than ±0.05 dB up to a frequency of 0.4 × f
provide the necessary peaking at the upper end of the pass band,
the inverse sinc filters shown have an intrinsic insertion loss of
about 3.2 dB. Figure 62 shows the composite frequency response.
The sinc
setting the bypass sinc
Figure 62. Sample Composite Responses of the Sinc
0x0000
20
15
10
5
0
–3.0
–3.2
–3.4
–3.6
–3.8
–4.0
−1
0
Figure 61. DAC Output Currents vs. DAC Offset Value
filter is disabled by default. It can be enabled by
0x4000
0.1
−1
−1
filter and the sin(x)/x response of the DAC
) filter is a nine-tap FIR filter. The composite
−1
DAC OFFSET VALUE
bit to 0 (Register 0x1B, Bit 6).
0x8000
0.2
f
OUT
/
f
DAC
0.3
0xC000
−1
Filter with sin(x)/x Roll-Off
0.4
0xFFFF
AD9122
DACCLK
0
5
10
15
20
0
.5
. To