LPC1820FET100 NXP Semiconductors, LPC1820FET100 Datasheet - Page 19

The LPC1820FET100 is a high-performance, cost-effective Cortex-M3 microcontroller featuring 168 kB of SRAM, and advanced peripherals including High Speed USB 2

LPC1820FET100

Manufacturer Part Number
LPC1820FET100
Description
The LPC1820FET100 is a high-performance, cost-effective Cortex-M3 microcontroller featuring 168 kB of SRAM, and advanced peripherals including High Speed USB 2
Manufacturer
NXP Semiconductors
Datasheet

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Part Number:
LPC1820FET100
Manufacturer:
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NXP Semiconductors
Table 3.
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See
LPC1850_30_20_10
Preliminary data sheet
Symbol
P2_12
P2_13
P3_0
Pin description
E15
C16
F13
x
x
x
…continued
B9
A10 156 108 75
A8
153 106 73
161 112
All information provided in this document is subject to legal disclaimers.
Rev. 3.1 — 15 December 2011
78
[3]
[3]
[3]
I; PU I/O GPIO1[12] — General purpose digital input/output
I; PU I/O GPIO1[13] — General purpose digital input/output
I; PU I/O I2S0_RX_SCK — I
O
-
I/O EMC_A3 — External memory address line 3.
-
-
-
I/O U2_UCLK — Serial clock input/output for USART2 in
I
-
I/O EMC_A4 — External memory address line 4.
-
-
-
I/O U2_DIR — RS-485/EIA-485 output enable/direction
O
I/O I2S0_TX_SCK — Transmit Clock. It is driven by the
O
I/O SSP0_SCK — Serial clock for SSP0.
-
-
-
Description
pin.
CTOUT_4 — SCT output 4. Match output 0 of
timer 1.
R — Function reserved.
R — Function reserved.
R — Function reserved.
R — Function reserved.
synchronous mode.
pin.
CTIN_4 — SCT input 4. Capture input 2 of timer 1.
R — Function reserved.
R — Function reserved.
R — Function reserved.
R — Function reserved.
control for USART2.
the master and received by the slave. Corresponds
to the signal SCK in the I
I2S0_RX_MCLK — I
master and received by the slave. Corresponds to
the signal SCK in the I
I2S0_TX_MCLK — I
R — Function reserved.
R — Function reserved.
R — Function reserved.
Table
32-bit ARM Cortex-M3 microcontroller
LPC1850/30/20/10
2.
2
S receive clock. It is driven by
2
2
S transmit master clock.
S receive master clock.
2
S-bus specification.
2
S-bus specification.
© NXP B.V. 2011. All rights reserved.
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