LPC1820FET100 NXP Semiconductors, LPC1820FET100 Datasheet - Page 63

• Manufacturer Part Number: LPC1820FET100
• Description: The LPC1820FET100 is a high-performance, cost-effective Cortex-M3 microcontroller featuring 168 kB of SRAM, and advanced peripherals including High Speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 3.
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See
LPC1850_30_20_10
Preliminary data sheet
Symbol
USB0_ID
USB0_RREF
USB1 pins
USB1_DP
USB1_DM
I
I2C0_SCL
I2C0_SDA
Reset and wake-up pins
RESET
WAKEUP0
WAKEUP1
WAKEUP2
WAKEUP3
ADC pins
ADC0_0/
ADC1_0/DAC
ADC0_1/
ADC1_1
ADC0_2/
ADC1_2
ADC0_3/
ADC1_3
ADC0_4/
ADC1_4
2
C-bus pins
Pin description
H2
H1
F12
G12
L15
L16
D9
A9
A10
C9
D8
E3
C3
A4
B5
C6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
…continued
F1
F3
E9
E10 130 90
D6
E6
B6
A4
-
-
-
A2
A1
B3
A3
-
132 92
133 93
187 130 93
30
32
129 89
185 128 91
-
-
-
8
4
206 143 99
200 139 96
199 138 -
All information provided in this document is subject to legal disclaimers.
22
24
-
-
-
6
2
Rev. 3.1 — 15 December 2011
13
15
59
60
62
63
-
-
-
4
1
[9]
[9]
[10]
[10]
[11]
[11]
[12]
[12]
[12]
[12]
[12]
[9]
[9]
[9]
[9]
[9]
-
-
-
-
I; F
I; F
I; IA
I; IA
I; IA
I; IA
I; IA
I; IA
I; IA
I; IA
I; IA
I; IA
I
I/O USB1 bidirectional D+ line.
I/O USB1 bidirectional D line.
I/O I
I/O I
I
I
I
I
I
I
I
I
I
I
External reset input: A LOW on this pin resets the
External wake-up input; can raise an interrupt and
External wake-up input; can raise an interrupt and
External wake-up input; can raise an interrupt and
External wake-up input; can raise an interrupt and
ADC input channel 0. Shared between 10-bit ADC0/1
ADC input channel 1. Shared between 10-bit
ADC input channel 2. Shared between 10-bit
ADC input channel 3. Shared between 10-bit
ADC input channel 4. Shared between 10-bit
Description
Indicates to the transceiver whether connected as an
A-device (USB0_ID LOW) or B-device (USB0_ID
HIGH). For OTG, this pin has an internal pull-up
resistor.
12.0 k (accuracy 1 %) on-board resistor to ground
for current reference.
compliance).
compliance).
device, causing I/O ports and peripherals to take on
their default states, and processor execution to begin
at address 0.
can cause wake-up from any of the low power
modes.
can cause wake-up from any of the low power
modes.
can cause wake-up from any of the low power
modes.
can cause wake-up from any of the low power
modes.
and DAC.
ADC0/1.
ADC0/1.
ADC0/1.
ADC0/1.
2
2
C clock input/output. Open-drain output (for I
C data input/output. Open-drain output (for I
Table
32-bit ARM Cortex-M3 microcontroller
LPC1850/30/20/10
2.
© NXP B.V. 2011. All rights reserved.
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2
2
C-bus
C-bus