LPC2921_23_25 NXP Semiconductors, LPC2921_23_25 Datasheet - Page 31

• Manufacturer Part Number: LPC2921_23_25
• Description: The LPC2921/2923/2925 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, Full-speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2921_23_25_3
Product data sheet
6.13.3.1 Pin description
6.14.1 Functional description
6.14 Modulation and Sampling Control SubSystem (MSCSS)
Table 19.
[1]
The Modulation and Sampling Control Subsystem (MSCSS) in the LPC2921/2923/2925
includes four Pulse Width Modulators (PWMs), two 10-bit successive approximation
Analog-to-Digital Converters (ADCs) and two timers.
The key features of the MSCSS are:
The MSCSS contains Pulse Width Modulators (PWMs), Analog-to-Digital Converters
(ADCs) and timers.
Figure 5
communication with the AHB system bus. Two internal timers are dedicated to this
subsystem. MSCSS timer 0 can be used to generate start pulses for the ADCs and the
first PWM. The second timer (MSCSS timer 1) is used to generate ‘carrier’ signals for the
PWMs. These carrier patterns can be used, for example, in applications requiring current
control. Several other trigger possibilities are provided for the ADCs (external, cascaded
or following a PWM). The capture inputs of both timers can also be used to capture the
start pulse of the ADCs.
Symbol
I2C SCL0/1
I2C SDA0/1
•
•
•
•
•
•
•
•
•
•
•
•
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
All I
Note that the pins are not I
Two 10-bit, 400 ksample/s, 8-channel ADCs with 3.3 V inputs and various trigger-
start options.
Four 6-channel PWMs (Pulse Width Modulators) with capture and trap functionality.
Two dedicated timers to schedule and synchronize the PWMs and ADCs.
Quadrature encoder interface.
2
C-bus controllers support multiple address recognition and a bus monitor mode.
provides an overview of the MSCSS. An AHB-to-APB bus bridge takes care of
2
C-bus can be used for test and diagnostic purposes.
I
2
C-bus pins
Pin name
SCL0/1
SDA0/1
All information provided in this document is subject to legal disclaimers.
[1]
Rev. 03 — 14 April 2010
2
C-bus compliant open-drain pins.
Direction
I/O
I/O
ARM9 microcontroller with CAN, LIN, and USB
Description
I
I
2
2
C clock input/output
C data input/output
LPC2921/2923/2925
© NXP B.V. 2010. All rights reserved.
31 of 84