EVX8AQ160TPY ETC-unknow, EVX8AQ160TPY Datasheet - Page 2

• Manufacturer Part Number: EVX8AQ160TPY
• Description: Adc Quad 1.25gsps 8-bit Lvds 380-pin Ebga
• Manufacturer: ETC-unknow

Screening
Applications
1. Block Diagram
2. Description
2
EV8AQ160
0846G–BDC–11/09
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•
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Figure 1-1.
The Quad ADC is constituted by four 8-bit ADC cores which can be considered independently (four-
channel mode) or grouped by two cores (two-channel mode with the ADCs interleaved two by two or
one-channel mode where all four ADCs are all interleaved).
All four ADCs are clocked by the same external input clock signal and controlled via an SPI (Serial
Peripheral Interface). An analog multiplexer (cross-point switch) is used to select the analog input
depending on the mode the Quad ADC is used.
The clock circuit is common to all four ADCs. This block receives an external 2.5 GHz clock (maximum
frequency) and preferably a low jitter symmetrical signal. In this block, the external clock signal is then
divided by two in order to generate the internal sampling clocks:
• In four-channel mode, the same 1.25 GHz clock is directed to all four ADC cores and T/H
• In two-channel mode, the in-phase 1.25 GHz clock is sent to ADC A or C and the inverted 1.25 GHz
Temperature Range for Packaged Device
Commercial C Grade: 0°C < T
High-speed Oscilloscopes
clock is sent to ADC B or D, while the analog input is sent to both ADCs, resulting in an interleaved
mode with an equivalent sampling frequency of 2.5 Gsps
2.5 GHz
Clock
Selection
Peripheral
Simplified Block Diagram
Interface
Clock
Buffer
Serial
SDA
+
+
Gain
amb
Offset
< 70°C
1:1 or 1:2 DMUX
Phase
LVDS Buffers
1.25 Gsps
ADC core
8-bit
T/H
Gain
Offset
1:1 or 1:2 DMUX
LVDS Buffers
1.25 Gsps
ADC core
Phase
(Cross Point Switch)
8-bit
T/H
Analog MUX
Gain
Offset
1:1 or 1:2 DMUX
LVDS Buffers
1.25 Gsps
ADC core
Phase
8-bit
T/H
Gain
e2v semiconductors SAS 2009
Offset
1:1 or 1:2 DMUX
LVDS Buffers
1.25 Gsps
ADC core
Phase
8-bit
T/H