EVX8AQ160TPY ETC-unknow, EVX8AQ160TPY Datasheet - Page 66
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EVX8AQ160TPY
Manufacturer Part Number
EVX8AQ160TPY
Description
Adc Quad 1.25gsps 8-bit Lvds 380-pin Ebga
Manufacturer
ETC-unknow
Datasheet
1.EVX8AQ160TPY.pdf
(82 pages)
- Current page: 66 of 82
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8.7.21
Table 8-43.
Table 8-45.
66
Bit 15
Bit 15
EV8AQ160
0846G–BDC–11/09
Bit 14
Bit 14
External Second Level INL Registers
External Second level INL Register Mapping: Address 0x33 to 0x34
External Second level INL Register Mapping: Address 0x35
Bit 13
Bit 13
Table 8-42.
Notes:
Applies to External second level INL registers A, B, C and D according to CHANNEL SELECTOR regis-
ter contents.
Table 8-44.
EXTERNAL INL2 X <7:0>
Table 8-46.
Notes:
Bit label
EXTERNAL INL1
X <7:0>
Bit label
EXTERNAL INL2
X <15:0>
Bit label
EXTERNAL INL2
X <7:0>
Bit 12
Bit 12
1. Actual first level INL of the selected channel is controlled by the transfer of External first level INL Regis-
2. Refer to the INL Calibration procedure for more information.
1. Actual second level INL of the selected channel is controlled by the transfer of External second level INL
2. Refer to the INL Calibration procedure for more information.
ter (addresses 0x30 to 0x32) upon request placed through the SPI in the CAL control register of the
selected channel.
Register (addresses 0x33 to 0x35) upon request placed through the SPI in the CAL control register of
the selected channel.
Bit 11
Bit 11
External First level INL Register Description
External Second Level INL Register Description
External Second Level INL Register Description
Value
0x00
0XFF
Value
0x0000
0XFFFF
Value
0x00
0XFF
Bit 10
Bit 10
(1)
EXTERNAL INL2 X <15:0>
Bit 9
Bit 9
Bit 8
Bit 8
Description
Description
Description
Bit 7
Bit 7
Bit 6
Bit 6
(1)
Bit 5
Bit 5
DO NOT USE (0x00)
Bit 4
Bit 4
Bit 3
Bit 3
e2v semiconductors SAS 2009
Bit 2
Bit 2
Default Setting
0x00
Default Setting
0x0000
Default Setting
0x00
Bit 1
Bit 1
Bit 0
Bit 0
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