HT46RU67 Holtek Semiconductor Inc., HT46RU67 Datasheet
HT46RU67
Related parts for HT46RU67
HT46RU67 Summary of contents
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... PFD function for sound generation Real Time Clock - RTC 8-bit RTC prescaler General Description The HT46RU67/HT46CU67 are 8-bit, high perfor- mance, RISC architecture microcontroller devices spe- cifically designed for A/D product applications that interface directly to analog signals and which require an LCD Interface. The HT46CU67, mask version device, is fully pin and functionally compatible with its sister HT46RU67 OTP device ...
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... Block Diagram Rev. 1.00 HT46RU67/HT46CU67 2 February 27, 2008 ...
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... Pin Assignment Rev. 1.00 HT46RU67/HT46CU67 3 February 27, 2008 ...
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... O or CMOS Output SEG24~SEG45 O Rev. 1.00 HT46RU67/HT46CU67 Description Bidirectional 8-bit input/output port. Each individual pin on this port can be configured as a wake-up input by a configuration option. Software in- structions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high re- sistors ...
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... Standby Current I STB1 (*f =T1) S Rev. 1.00 HT46RU67/HT46CU67 Description An LCD duty-cycle configuration option determines if SEG46 is config- ured as a segment driver common output driver for the LCD panel. COM0~COM2 are the LCD common outputs. Reference voltage input pin. Schmitt Trigger reset input. Active low. ...
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... ADC Input Reference Voltage V REF Range I/O Port Segment Logic Output I OL1 Sink Current I/O Port Segment Logic Output I OH1 Source Current Rev. 1.00 HT46RU67/HT46CU67 Test Conditions Min. V Conditions DD No load, system HALT, 3V LCD On at HALT, C type, 5V UART Off No load, system HALT, 3V LCD On at HALT, C type, ...
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... System Start-up Timer Period SST t Low Voltage Width to Reset LVR t Interrupt Pulse Width INT t A/D Clock Period AD t A/D Conversion Time ADC t A/D Sampling Time ADCS Note 1/f or 1/f SYS SYS1 SYS2 Rev. 1.00 HT46RU67/HT46CU67 Test Conditions V Conditions =0. =0. ...
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... S14 S13 S12 S11 S10 S9 Note: *14~*0: Program counter bits #12~#0: Instruction code bits Rev. 1.00 HT46RU67/HT46CU67 Program Counter - PC The program counter is 15 bits wide and controls the se- quence in which the instructions stored in the program ROM are executed. The contents of the PC can specify a maximum of 32768 16 addresses. ...
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... Note: *14~*0: Table location bits @7~@0: Table pointer lower-order bits (TBLP) Rev. 1.00 HT46RU67/HT46CU67 Certain locations in the Program Memory are reserved for special usage: Location 000H Location 000H is reserved for program initialisation. After a device reset, the program will jump to this loca- tion and begin execution. ...
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... The stack register is a special part of the memory used to save the contents of the program counter. The stack is organized into 16 levels and is neither part of the data Rev. 1.00 HT46RU67/HT46CU67 nor part of the program, and is neither readable nor writeable. Its activated level is indexed by a stack pointer, known as SP, which is neither readable nor writeable ...
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... RAM Mapping Rev. 1.00 HT46RU67/HT46CU67 Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write op- eration of [00H] and [02H] accesses the Data Memory pointed to by MP0 and MP1 respectively. Reading loca- tion 00H or 02H indirectly returns the result 00H. Writing to it indirectly results to no operation ...
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... External interrupts are triggered by an edge transition Rev. 1.00 HT46RU67/HT46CU67 Function Status (0AH) Register on pins INT0 or INT1 . A configuration option exists to select one of three transition types, either high to low, low to high or both. The related interrupt request flag, EIF0 ...
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... RTF Real time clock interrupt request flag (1=active; 0=inactive) Rev. 1.00 HT46RU67/HT46CU67 MFIC register, caused by a regular real time clock time-out, RTF; bit 6 of the MFIC register or caused by a time base time-out, TBF; bit5 of the MFIC register. After the interrupt is enabled, EMFI=1, the stack is not full, and the MFF bit is set, a subroutine call to location 018H will occur ...
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... However, the frequency of the oscillation may vary with VDD, temper- ature, and the chip itself due to process variations therefore, not suitable for timing sensitive operations where accurate an oscillator frequency is desired. System Oscillator 14 HT46RU67/HT46CU67 The sys- February 27, 2008 ...
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... If the WDT time-out is selected maximum time-out period is divided by 2 Rev. 1.00 HT46RU67/HT46CU67 give a time of about 2.1s~4.3s for the internal WDT os- cillator. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock. The WDT will operate in the same manner except that in the Power Down mode, the WDT will stop counting and lose its pro- tecting purpose ...
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... However wake-up results in the next instruction execution, the execution will be performed * immediately after the dummy period has finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the Power Down state. 16 HT46RU67/HT46CU67 (system SYS February 27, 2008 ...
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... SST (System Start-up Timer) provides an extra delay of 1024 system clock pulses when the sys- tem awakens from the Power Down mode or during power up. Reset Timing Chart Rev. 1.00 HT46RU67/HT46CU67 The functional unit chip reset status is shown below. Program Counter 000H Interrupt Disabled ...
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... HT46RU67/HT46CU67 RES Reset WDT Time-out (HALT) (HALT)* uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 00u0 00uu uuuu uuuu uuuu uuuu ...
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... T0ON/T1ON/ T2ON is auto- matically cleared after a measurement cycle is com T0ON/T1ON/T2ON can only be reset by instructions. 19 HT46RU67/HT46CU67 RES Reset WDT Time-out (HALT) (HALT)* 0000 00x0 ...
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... Set- Rev. 1.00 HT46RU67/HT46CU67 ting the timer enable bit high together with a modification, may lead to improper timer operation if ex- ecuted as a single timer control register byte write in- struction ...
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... Defines the operating mode, T0M1, T0M0: 01=Event count mode (external clock) 6 T0M0 10=Timer mode (internal clock) 7 T0M1 11=Pulse width measurement mode 00=Unused Rev. 1.00 Timer/Event Counter 2 PFD Source Option Function SYS /2 SYS /4 SYS /8 SYS /16 SYS /32 SYS /64 SYS /128 SYS TMR0C (0EH) Register 21 HT46RU67/HT46CU67 February 27, 2008 ...
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... Defines the operating mode, T2M1, T2M0: 01=Event count mode (external clock) 6 T2M0 10=Timer mode (internal clock) 7 T2M1 11=Pulse width measurement mode 00=Unused Rev. 1.00 Function TMR1C (11H) Register Function SYS /2 SYS /4 SYS /8 SYS /16 SYS /32 SYS /64 SYS /128 SYS TMR2C (2EH) Register 22 HT46RU67/HT46CU67 February 27, 2008 ...
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... Logical Input Note: ThePFDfrequency isthetimer/event counter overflow frequency divided by2. Rev. 1.00 HT46RU67/HT46CU67 the pull-high configuration options. Each bit of these in- put/output latches can be set or cleared by the SET [m].i and CLR [m].i bit manipulation instructions. Some instructions first input data and then follow the out- put operations ...
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... X stands for unused U stands for unknown M is 65536 for PFD0 or PFD1 N is the preload value for the timer/event counter f is input clock frequency for timer/event counter TMR Rev. 1.00 HT46RU67/HT46CU67 O/P (Normal) I/P (PWM) Logical Output Logical Input PA3 Data Register PA3 Pad State 0 ...
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... PWM1 and PWM2. Devices with four PWM outputs re- quire a further additional register known as PWM3 here that the 8-bit value, which represents the overall Rev. 1.00 HT46RU67/HT46CU67 PC6/TX Input/Output Ports PC7/RX Input/Output Ports duty cycle of one modulation cycle of the output wave- form, should be placed. To increase the PWM modula- ...
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... PWM operation impor- tant to note how the single PWM cycle is subdivided into 4 individual modulation cycles, numbered from 0~3 and how the AC value is related to the PWM value. 6+2 Mode PWM Register 26 HT46RU67/HT46CU67 PWM Register Name PWM0/PWM1/PWM2 PWM0/PWM1/PWM2/PWM3 AC (0~3) Duty Cycle i< ...
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... After these two initial steps have been carried out, and of course after the required PWM value has been written into the PWM register, writing the corresponding bit in the PD output data register will en- Rev. 1.00 HT46RU67/HT46CU67 Parameter Modulation cycle i (i=0~1) 7+1 Mode Modulation Cycle Values The following diagram illustrates the waveforms asso- ciated with the 7+1 mode PWM operation ...
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... PB can be an analog input or setup as a normal I/O line, the selected function is determined by these 3 bits. Once a PB line is selected as an analog in- put, the I/O function and pull-high resistor of this I/O line Rev. 1.00 HT46RU67/HT46CU67 PD.0 will remain low PD.1 will remain low PD.2 will remain low PD.3 will remain low are disabled and the A/D converter circuit is pow- ered-on ...
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... AN4 AN3 PB6 AN5 AN4 AN3 AN6 AN5 AN4 AN3 Port B Configuration Bit5 Bit4 Bit3 ADRL (24H), ADRH (25H) Register 29 HT46RU67/HT46CU67 PB2 PB1 PB0 PB2 PB1 AN0 PB2 AN1 AN0 AN2 AN1 AN0 AN2 AN1 AN0 AN2 AN1 ...
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... ADRL register mov adrl_buffer,a ; save result to user defined memory : : jmp start_conversion ; start next A/D conversion Rev. 1.00 HT46RU67/HT46CU67 /8 as the A/D clock SYS A/D Conversion Timing 30 February 27, 2008 ...
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... MAX else V connect to V MAX Rev. 1.00 HT46RU67/HT46CU67 and written to only by indirect addressing mode using MP1. When data is written into the LCD display mem- ory automatically read by the LCD driver which then generates the corresponding LCD driving signals. To turn the display on or off written to the corresponding bit of the display memory, respectively ...
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... LCD Driver Output (1/3 Duty, 1/2 Byte, R/C Type) Rev. 1.00 HT46RU67/HT46CU67 32 February 27, 2008 ...
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... Rev. 1.00 HT46RU67/HT46CU67 LCD Driver Output 33 February 27, 2008 ...
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... To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay, the device enters the reset mode. Rev. 1.00 HT46RU67/HT46CU67 Function RTCC (09H) Register The relationship between V Note: V ...
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... UART Bus Serial Interface The HT46RU67/HT46CU67 devices contain an inte- grated full-duplex asynchronous serial communications UART interface that enables communication with exter- nal devices that contain a serial interface. The UART function has many features and can transmit and re- ceive data serially by transferring a frame of data with ...
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... NF, FERR, and/or PERR are set within the same clock cycle. The Rev. 1.00 HT46RU67/HT46CU67 RXIF flag is cleared when the USR register is read with RXIF set, followed by a read from the RXR reg- ister, and if the RXR register has no data available. ...
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... STOPS This bit determines if one or two stop bits are to be used. When this bit is equal to 1 two stop bits are Rev. 1.00 HT46RU67/HT46CU67 used, if the bit is equal to 0 then only one stop bit is used. PRT This is the parity type selection bit. When this bit is equal to 1 odd parity will be selected, if the bit is equal to 0 then even parity will be selected ...
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... If this bit is equal to 1 and if the MCU is in the Power Down Mode, a low going edge on the RX input pin will wake-up the device. If this bit is equal Rev. 1.00 HT46RU67/HT46CU67 to 0 and if the MCU is in the Power Down Mode, any edge transitions on the RX pin will not wake-up the device. ...
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... BR [64(12 + 1)] Therefore the error is equal SYS [ 1)] Baud Rates for BRGH=0 =4MHz Error (%) BRG 0.00 185 0.16 46 0.16 22 0.16 11 -6. HT46RU67/HT46CU67 f SYS 1 (BRx64) 4000000 1 12.0208 x ( 4800 64 ) 4808 = 0.16% f =3.579545MHz SYS Error (%) Kbaud 0.300 0.00 1.19 -0.83 2.432 1.32 4.661 -2.9 9.321 -2.9 18 ...
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... The fol- lowing table shows various formats for data trans- mission. The address bit identifies the frame as an address character. The number of stop bits, which can be either one or two, is independent of the data length. 40 HT46RU67/HT46CU67 f =3.579545MHz SYS Kbaud Error (%) 1.203 ...
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... The TX output pin will then return to having a normal general purpose I/O pin function. Rev. 1.00 HT46RU67/HT46CU67 Transmitting data Stop When the UART is transmitting data, the data is Bit shifted on the TX pin from the shift register, with the least significant bit first ...
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... Setup the BRG register to select the desired baud rate. Rev. 1.00 HT46RU67/HT46CU67 Set the RXEN bit to ensure that the RX pin is used as a UART receiver pin and not as an I/O pin. At this point the receiver will be enabled which will begin to look for a start bit ...
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... Data will be transferred from the Shift register to the RXR register. No interrupt will be generated. However this bit Rev. 1.00 HT46RU67/HT46CU67 rises at the same time as the RXIF bit which itself generates an interrupt. Note that the NF flag is reset by a USR register read operation followed by an RXR register read operation ...
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... The address detect mode and parity enable are mutually exclusive functions. Therefore if the address detect Rev. 1.00 HT46RU67/HT46CU67 mode is enabled, then to ensure correct operation, the parity function should be disabled by resetting the par- ity enable bit to zero. ...
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... SBDR Master clock sending started by writing SBDR Slave transmitter: data I/O started by clock received Slave receiver: data I/O started by clock received 45 HT46RU67/HT46CU67 serial bus selection signal en- this bit is set data is written to data transferred or data received write data to TXRX buffer read from SBDR only ...
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... CLK signal is set and slave data transfer- ring should be disabled (or enabled) before (after) SCS signal is received. CSEN= 0, SCS signal is not needed, Rev. 1.00 HT46RU67/HT46CU67 Operations data is stored in TXRX buffer output CLK (and SCS) signals data stored in TXRX buffer, and SDI data is shifted into TXRX clear WCOL and go to step 4 ...
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... Rev. 1.00 HT46RU67/HT46CU67 47 February 27, 2008 ...
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... LCD Segments as logical output selection, (byte, byte, bit, bit, bit, bit, bit, bit, bit, bit option) [SEG0~SEG7], [SEG8~SEG15], SEG16, SEG17, SEG18, SEG19, SEG20, SEG21, SEG22, or SEG23 LVR selection. LVR has enable or disable options LVD selection. LVD has enable or disable options Rev. 1.00 HT46RU67/HT46CU67 Options ...
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... INT1, 14H: SIO SIO selection. SIO has enable a disable options SIO WCOL selection. SIO WCOL has enable or disable options. SIO CSEN selection. SIO CSEN has enable or disable options. SIO CPOL selection. SIO CPOL has enable or disable options. Rev. 1.00 HT46RU67/HT46CU67 Options 49 February 27, 2008 ...
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... RES pin is kept as short as possible, to avoid noise interference. 3. For applications where noise may interfere with the reset circuit and for details on the oscillator external com- ponents, refer to Application Note HA0075E for more information. Rev. 1.00 HT46RU67/HT46CU67 50 February 27, 2008 ...
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... Within the Holtek microcontroller instruction set are a range of add and Rev. 1.00 HT46RU67/HT46CU67 subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to en- sure correct handling of carry and borrow data when re- sults exceed 255 for addition and less than 0 for subtraction ...
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... DECA [m] Decrement Data Memory with result in ACC DEC [m] Decrement Data Memory Rev. 1.00 HT46RU67/HT46CU67 Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT in- struction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electro- magnetic environments ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 HT46RU67/HT46CU67 Description 53 Cycles Flag Affected ...
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... Operation ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 1.00 HT46RU67/HT46CU67 54 February 27, 2008 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 1.00 HT46RU67/HT46CU67 addr 55 February 27, 2008 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 1. HT46RU67/HT46CU67 February 27, 2008 ...
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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 1.00 HT46RU67/HT46CU67 addr 57 February 27, 2008 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 1.00 Stack Stack Stack [m]. 0~6) 58 HT46RU67/HT46CU67 February 27, 2008 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 1.00 [m]. 0~6) 59 HT46RU67/HT46CU67 February 27, 2008 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 1.00 [ HT46RU67/HT46CU67 February 27, 2008 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 1.00 0 [m] [ HT46RU67/HT46CU67 February 27, 2008 ...
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... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev. 1.00 HT46RU67/HT46CU67 [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 62 February 27, 2008 ...
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... The result is stored in the Data Memory. Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 1.00 HT46RU67/HT46CU67 63 February 27, 2008 ...
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... Package Information 52-pin QFP (14´14) Outline Dimensions Symbol Rev. 1.00 HT46RU67/HT46CU67 Dimensions in mm Min. Nom. 17.3 13.9 17.3 13.9 1 0.4 2.5 0.1 0.73 0 Max. 17.5 14.1 17.5 14.1 3.1 3.4 1.03 0.2 7 February 27, 2008 ...
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... SSOP (300mil) Outline Dimensions Symbol Rev. 1.00 HT46RU67/HT46CU67 Dimensions in mil Min. Nom. 395 291 8 720 Max. 420 299 12 730 February 27, 2008 ...
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... QFP (14´20) Outline Dimensions Symbol Rev. 1.00 Dimensions in mm Min. Nom. 18.50 13.90 24.50 19.90 0.65 0.30 2.50 0. HT46RU67/HT46CU67 Max. 19.20 14.10 25.20 20.10 3.10 3.40 1.40 0.20 7 February 27, 2008 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 HT46RU67/HT46CU67 67 February 27, 2008 ...