HT46RU67 Holtek Semiconductor Inc., HT46RU67 Datasheet - Page 42

• Manufacturer Part Number: HT46RU67
• Description: Ht46ru67/ht46cu67 -- A/d Type 8-bit Mcu With Lcd
• Manufacturer: Holtek Semiconductor Inc.

Rev. 1.00
UART receiver
If the TXBRK bit is set then break characters will be
sent on the next transmission. Break character
transmission consists of a start bit, followed by 13
N 0 bits and stop bits, where N=1, 2, etc. If a break
character is to be transmitted then the TXBRK bit
must be first set by the application program, then
cleared to generate the stop bits. Transmitting a
break character will not generate a transmit inter-
rupt. Note that a break condition length is at least 13
bits long. If the TXBRK bit is continually kept at a
logic high level then the transmitter circuitry will
transmit continuous break characters. After the ap-
plication program has cleared the TXBRK bit, the
transmitter will finish transmitting the last break
character and subsequently send out one or two
stop bits. The automatic logic highs at the end of the
last break character will ensure that the start bit of
the next frame is recognized.
The UART is capable of receiving word lengths of ei-
ther 8 or 9 bits. If the BNO bit is set, the word length
will be set to 9 bits with the MSB being stored in the
RX8 bit of the UCR1 register. At the receiver core lies
the Receive Serial Shift Register, commonly known
as the RSR. The data which is received on the RX
external input pin, is sent to the data recovery block.
The data recovery block operating speed is 16 times
that of the baud rate, while the main receive serial
shifter operates at the baud rate. After the RX pin is
sampled for the stop bit, the received data in RSR is
transferred to the receive data register, if the register
is empty. The data which is received on the external
RX input pin is sampled three times by a majority de-
tect circuit to determine the logic level that has been
placed onto the RX pin. It should be noted that the
RSR register, unlike many other registers, is not di-
rectly mapped into the Data Memory area and as
such is not available to the application program for
direct read/write operations.
When the UART receiver is receiving data, the data
is serially shifted in on the external RX input pin,
LSB first. In the read mode, the RXR register forms
a buffer between the internal bus and the receiver
shift register. The RXR register is a two byte deep
FIFO data buffer, where two bytes can be held in the
FIFO while a third byte can continue to be received.
Note that the application program must ensure that
the data is read from RXR before the third byte has
been completely shifted in, otherwise this third byte
will be discarded and an overrun error OERR will be
subsequently indicated. The steps to initiate a data
transfer can be summarized as follows:
Transmit break
Introduction
Receiving data
Make the correct selection of BNO, PRT, PREN
and STOPS bits to define the word length, parity
type and number of stop bits.
Setup the BRG register to select the desired baud
rate.
42
At this point the receiver will be enabled which will
begin to look for a start bit.
When a character is received the following se-
quence of events will occur:
The RXIF bit can be cleared using the following soft-
ware sequence:
Any break character received by the UART will be
managed as a framing error. The receiver will count
and expect a certain number of bit times as speci-
fied by the values programmed into the BNO and
STOPS bits. If the break is much longer than 13 bit
times, the reception will be considered as complete
after the number of bit times specified by BNO and
STOPS. The RXIF bit is set, FERR is set, zeros are
loaded into the receive data register, interrupts are
generated if appropriate and the RIDLE bit is set. If
a long break signal has been detected and the re-
ceiver has received a start bit, the data bits and the
invalid stop bit, which sets the FERR flag, the re-
ceiver must wait for a valid stop bit before looking
for the next start bit. The receiver will not make the
assumption that the break condition on the line is
the next start bit. A break is regarded as a character
that contains only zeros with the FERR flag set. The
break character will be loaded into the buffer and no
further data will be received until stop bits are re-
ceived. It should be noted that the RIDLE read only
flag will go high when the stop bits have not yet
been received. The reception of a break character
on the UART registers will result in the following:
When the receiver is reading data, which means it
will be in between the detection of a start bit and the
reading of a stop bit, the receiver status flag in the
USR register, otherwise known as the RIDLE flag,
will have a zero value. In between the reception of a
stop bit and the detection of the next start bit, the
RIDLE flag will have a high value, which indicates
the receiver is in an idle condition.
Receive break
Idle status
1. A USR register access
2. An RXR register read execution
Set the RXEN bit to ensure that the RX pin is used
as a UART receiver pin and not as an I/O pin.
The RXIF bit in the USR register will be set when
RXR register has data available, at least one
more character can be read.
When the contents of the shift register have been
transferred to the RXR register, then if the RIE bit
is set, an interrupt will be generated.
If during reception, a frame error, noise error, par-
ity error, or an overrun error has been detected,
then the error flags can be set.
The framing error flag, FERR, will be set.
The receive data register, RXR, will be cleared.
The OERR, NF, PERR, RIDLE or RXIF flags will
possibly be set.
HT46RU67/HT46CU67
February 27, 2008