HT46RU67 Holtek Semiconductor Inc., HT46RU67 Datasheet - Page 20

• Manufacturer Part Number: HT46RU67
• Description: Ht46ru67/ht46cu67 -- A/d Type 8-bit Mcu With Lcd
• Manufacturer: Holtek Semiconductor Inc.

The overflow of the Timer/Event Counter 0/1/2 is one of
the wake-up sources. The Timer/Event Counter 0/1 can
also be applied to a PFD or Programmable Frequency
Divider whose output is on pin PA3 via a configuration
option. Only one PFD (PFD0 or PFD1) can be applied to
PA3 by options. No matter what the operation mode is,
writing a 0 to ET0I, ET1I or ET2I disables the related
interrupt service. When the PFD function is selected, ex-
ecuting the SET [PA].3 instruction will enable the PFD
output and executing the CLR [PA].3 instruction will
disable the PFD output.
If the timer/event counter is not running, writing data to
the timer/event counter preload register will also reload
that data to the timer/event counter. But if the
timer/event counter running, data written to the
timer/event counter is kept only in the timer/event coun-
ter preload register. The timer/event counter continues
to operate until an overflow occurs at which point the
new data will be loaded from the preload register into the
timer/event counter.
After the timer has been initialised the timer can be
turned on and off by controlling the enable bit in the
timer control register.
bit high to turn the timer on, should only be executed af-
ter the timer mode bits have been properly setup. Set-
Rev. 1.00
Note that setting the timer enable
Timer/Event Counter 0
Timer/Event Counter 1
20
ting the timer enable bit high together with a
modification, may lead to improper timer operation if ex-
ecuted as a single timer control register byte write in-
struction.
When the timer/event counter is read, the clock is
blocked to avoid errors. As this may results in a counting
error, blocking of the clock should be taken into account
by the programmer.
It is strongly recommended to load a desired value into
the TMR0/TMR1/TMR2 registers first, before turning on
the related timer/event counter, for proper operation
since the initial value of the TMR0/TMR1/TMR2 regis-
ters are unknown. Due to the timer/event counter
scheme, the programmer should pay special attention
to the instruction to enable then disable the timer for the
first time, whenever there is a need to use the
timer/event counter function, to avoid unpredictable re-
sult. After this procedure, the timer/event counter func-
tion can be operated normally.
The bit0~bit2 of the TMR0C/TMR2C (T0PSC2~0/
T2PSC2~0) can be used to define the pre-scaling
stages of the internal clock sources of the timer/event
counter. The overflow signal of the timer/event counter
can be used to generate the PFD signal. The timer
prescaler is also used as the PWM counter.
HT46RU67/HT46CU67
February 27, 2008
mode bit