S5D2650 Samsung Semiconductor, Inc., S5D2650 Datasheet
S5D2650
Available stocks
Related parts for S5D2650
S5D2650 Summary of contents
Page 1
... CCIR 601 or square pixel sample rates in either YCbCr or RGB formats. The digital video can be scaled down in both the horizontal and vertical directions. The S5D2650 also decodes Intercast, Teletext, Closed Caption, and SMPTE data with a built-in bit data slicer. Digitized CVBS data can be output directly during VBI for external processing ...
Page 2
... S5D2650 Data Sheet BLOCK DIAGRAM ELECTRONICS MULTIMEDIA VIDEO PAGE 7/18/03 ...
Page 3
... S5D2650 Data Sheet PIN ASSIGNMENT - 100 PQFP # # # # % % $ # % % $ # # % % $ # $ # $ $ $ $ # % % $ $ $ % # $ $ $ # $ $ % # # % % $ # $ $ $ # $ $ $ # # $ $ $ # % % % % % % $ % % # $ $ % ...
Page 4
... S5D2650 Data Sheet PIN DESCRIPTI O N Pin Name Pin # ANALOG PINS, Reference CLOCK and RESET AY0 84 AY1 86 ACR0 88 ACR1 90 ACB0 92 ACB1 94 COMP2 97 FILT 99 XTALI 7 XTALO 8 RSTB 10 INPUT, OUTPUT and Bi-Directional Pins (All output pins can be selectively tri-stated Y7 45-48,53-56,33- 39,44 EXV0 - EXV7 ...
Page 5
... S5D2650 Data Sheet PIN DESCRIPTION (Continued) Pin Name Pin # PID 17 OEN CK2 21 CCDAT 73 CCEN 74 MULTI-PURPOSE I/O PORTS PORTA 58 PORTB(SCH) 24 HOST INTERFACE SCLK 75 SDAT 72 AEX0 - AEX1 POWER AND GROUND VDD3 9,20,59 VDD1 11,12,42,43,66, 67 VDDA 85,89,93 VDDP 98 VSS 1,2,6,13,14,19, 40,41,49-52,60, 64,65,77-80, 81-83,87,91,95, 96 VSSP 100 ELECTRONICS Type O PAL ID flag. Pahse Alternate Line flag I Output data, timing and clock 3-state output control ...
Page 6
... S5D2650 Data Sheet PIN DESCRIPTION (Continued) Pin Name Pin # TEST TEST0 29 TEST1 30 TEST2 57 SCANEN 31 CKE 32 ELECTRONICS Type I Test pin 0. For normal use, this pin should be connected to VSS. I Test pin 1. For normal use, this pin should be connected to VSS. I Test pin 2. For normal use, this pin should be connected to VSS. ...
Page 7
... S5D2650 Data Sheet PIN CROSS REFERENCE: NUMERICAL ORDER BY PIN NUMBER Pin # Pin Name 1 VSS 2 VSS 3 VAV 4 EVAV 5 EHAV 6 VSS 7 XTALI 8 XTALO 9 VDD3 10 RST 11 VDD1 12 VDD1 13 VSS 14 VSS 15 OEN 16 EXV0 17 PID VSS 20 VDD3 21 CK2 22 ODD PORTB(SCH) 25 HAV ELECTRONICS Pin # Pin Name ...
Page 8
... The analog inputs must be AC coupled through an external 0.1 mF capacitor clamp. Due to the high sampling rate of the ADC’s inside the S5D2650, most video sources will not require a low-pass filter for alias reduction. For those video sources with harmonics above 13 MHz, a simple single order pole at 6 MHz will provide sufficient high ...
Page 9
... The S5D2650 accepts CCIR 656 compliant 8-bit YCbCr digital video input with embedded or external HS, VS timing. Video timing may also be generated by the S5D2650. Data path for 8-bit YCbCr input is shown in Figure 3. Selection of analog video input or digital CCIR 656 data is with the INPSL[1:0] register bits. ...
Page 10
... Pixel Clock and Timing Mode Selection for Digital Video Input Pixel clock and synchronization timing can be individually selected to either come from an external generator or be generated internally. In addition, if synchronization is provided by an external source, the S5D2650 supports embedded syncs as defined in CCIR 656, or TTL HS and VS inputs. Selection of pixel clock is via CKDIR bit in CMDD register ...
Page 11
... Figure 4. 1.1.5. Additional Information for Analog Component Video Input For the S5D2650 to correctly set the V component phase in PAL mode analog component video input mode, PORTA (pin 58) need to be connected VSS. PORTA has to be configured as input (DIRA = 0) and connected to the internal CBG signal (DATAA[2:0] = 3). Also S5D2650 supports progressive analog component input. ...
Page 12
... The sampling clock is generated by multiplying the line rate by N. This ensures that samples are aligned horizontally, vertically and in time. The required N factor for the S5D2650 is based upon the field rate ( Hz) and the desired sampling rates (CCIR 601 or square pixel). Field rate can be automatically detected and can be monitored with the FFRDET bit in the STAT register ...
Page 13
... The S5D2650 can generate all the video timing without video input. This enables the S5D2650 to be used as a video timing generator for a system that contains both the S5D2650 for live video input and a MPEG decoder which requires a video timing generator ...
Page 14
... S5D2650 Data Sheet Table 4: Horizontal Timing Signal Edge Locations ( CK) Description Chip delay Sync gate (1-CK pulse) Back porch gate Color burst gate (1-CK pulse) Wide color burst gate Two pulses per line (1-CK each pulse) Chrominance offset duration Default horizontal sync(int.) Default horizontal active(int.) An additional signal, HAV, is provided for horizontal video cropping ...
Page 15
... PAL) the phase of the color burst relative to the sync tip must be measured. That information is provided by the PORTB(SCH) pin. The S5D2650 provides the output of a comparator that measures whether the current color burst phase relative to the falling edge of the sync is greater or less than a predetermined constant. This constant is controlled with SCHCMP[3:0] ...
Page 16
... S5D2650 Data Sheet SCHCMP[3:0] value. The SCH signal changes every video line. The SCH for line 260 is held for the entire vertical blanking period. By using the SCH signal for the same line from each field, proper field identification can be determined. Figure 8 shows field identification values for SCHCMP[3:0]= important to note that the SCH value is only valid for video signals that have a constant sync tip to color burst relationship ...
Page 17
... By noting this value at the same line of each field, a determination of whether a field is from {1-4} or {5-8} can be made. As with the SCH pin, the S5D2650 is designed to hold the line 260 PID measurement for the entire vertical blank period. This allows easy sampling of the PID or current field identification. ...
Page 18
... Figure 11. 1.3.1. Luminance DC Gain The S5D2650 can accommodate CCIR 624 M/N/H/G standards, which fall into categories of -40 or -43 sync tip and inclusion or exclusion of 7.5 setup. The S5D2650 can produce correct CCIR 601 luminance output levels by controlling the gain and offset in the luminance path via PED. This register should be set for the appropriate input standard ...
Page 19
... S5D2650 Data Sheet M ax Input Peak W hite B lack Level B lanking Level Luminance levels produced by the S5D2650 for different broadcast standards (assuming AGCGN=0, CONT=0 and BRT=0) are summarized in Table 5. Table 5: Luminance Digital Level Code M/N PED=1 Level Signal (IRE) (CVBS) Max Input 109 ...
Page 20
... HYLPF[2:0] provides the necessary bandwidth reduction for horizontal scaling. When all three registers are programmed to “0”, the decimation filter has the bandwidth of the normal video. The S5D2650 provides the option of bypassing the decimation filter. This option should be used only when the input video is band limited and with low high frequency noise. For composite video input, the notch filter can be enabled (CTRAP set to “ ...
Page 21
... S5D2650 Data Sheet Figure 13. Medium to High Frequency Luma Filter Characteristics (CTRAP=0) Figure 14. Medium to Low Frequency Luma Filter Characteristics (NTSC, CTRAP=1) ELECTRONICS MULTIMEDIA VIDEO PAGE 7/18/03 ...
Page 22
... S5D2650 Data Sheet Figure 15. Medium to Low Frequency Luma Filter Characteristic (PAL, CTRAP=1) Figure 16. Luma Filter Characteristic with Peaking On (NTSC, CTRAP=1) ELECTRONICS MULTIMEDIA VIDEO PAGE 7/18/03 ...
Page 23
... Control FROM ADC Figure 17. The S5D2650 supports chroma input in NTSC, PAL, SECAM and component formats. The color standard is automatically detected and the various chroma processing blocks are enabled as required for the given chroma standard. Details of the various chroma processing blocks follow. ...
Page 24
... S5D2650 Data Sheet Figure 18. 1.4.2. Demodulation Gain The demodulation gain block is controlled by feedback from the gain tracking block. For NTSC and PAL type inputs, the gain constant is derived from a programmable reference compared against the U component of the input video. This reference is controlled by the SAT register. The default value “0” is the correct gain (saturation for nominal output). For SECAM type input, the feedback is calculated such that proper frequency demodulation is obtained. When external calibration is desired, the gain feed back loop can be “ ...
Page 25
... S5D2650 Data Sheet Figure 19. 1.4.4. SECAM Demodulation SECAM processing includes a frequency differentiator, a Cloche and a de-emphasis filter. Frequency response for the filters are shown in Figure 20 and Figure 21. Figure 20. ELECTRONICS Chroma Low Pass Filter Frequency Response Cloche Filter Frequency Characteristic MULTIMEDIA VIDEO PAGE ...
Page 26
... S5D2650 Data Sheet Figure 21. 1.4.5. Additional Chroma Functions S5D2650 has many built in auto detection circuits. These allow S5D2650 to track any type of video standard input automatically. For analog component video input, the demodulation function is not enabled. The low pass filter provides a group delay for Cb and Cr alignment. This enables the two components to be sampled by one ADC. ...
Page 27
... Chroma 1.5.1. Luma Comb Filter The luma comb filter reduces high frequency chroma leakage into the luminance path. The S5D2650 uses 2-line stored luma data for combing. Filter coefficients for different video input standards are provided and can be selected automatically based on the video input. Filter coefficients may also be set manually. ...
Page 28
... S5D2650 Data Sheet 1.6. SCALING The S5D2650 includes a high quality down scaler. The video images can be down scaled in both horizontal and vertical direction to an arbitrary size. 1.6.1. Horizontal Scaler The horizontal scaler uses a 5-tap 32-phase interpolation filter for luma, and a 3-tap 8-phase interpolation filter for chroma ...
Page 29
... S5D2650 Data Sheet Figure 24. Horizontal Luma Scaler Interpolation Filter Frequency Response 3 2.5 2 1.5 1 Figure 25. Because of the limited bandwidth of the chroma data, a simpler interpolation filter is used for the horizontal chroma scaler. The frequency response and group delay for this filter are shown in Figure 26 and Figure 27, respectively. ...
Page 30
... S5D2650 Data Sheet Figure 26. Horizontal Chroma Scaler Interpolation Filter Frequency Response 1.5 1.0 0.5 Figure 27. ELECTRONICS Horizontal Chroma Scaler Interpolation Filter Group Delay MULTIMEDIA VIDEO PAGE 7/18/03 ...
Page 31
... VAVOD0, VAVEV0, and VSCL are programmed such that the vertical interpolation filter has the same phase and scaling ratio as that of a memory controller (most memory controller has simple line dropping vertical scaling possible to interface the S5D2650 to the memory controller without using EVAV. 1.6.3. Chroma Vertical Scaling Chroma vertical scaling uses different algorithms depending on video input standard and horizontal scaling ratio. If horizontal scaling results in line with less than or equal to 384 pixels, and the VRT2X is set to a “ ...
Page 32
... S5D2650 Data Sheet NTSC input, and decimation (line dropping without filtering) will be used for PAL and SECAM. Filter characteristics for the 3-tap and 5-tap filters are shown in Figure 29. Figure 29. Chroma Vertical Scaler Interpolation Filter Frequency Response ELECTRONICS MULTIMEDIA VIDEO PAGE ...
Page 33
... Copy Generation Management System (EIA/IS-702) • Wide Screen Signalling (WSS ETS 300 294). Note that the SMPTE data slicing is removed for the S5D2650 and replaced with the WSS / CGMS processing. This data can be accessed from the part via four different methods: • ...
Page 34
... S5D2650 Data Sheet Table 7 lists all the video standards that the VBI data slicer supports. Some of these modes are auto detected based on the current video input standard, Table 7: Video Standards Supported by VBI Decoder Mode 60Hz Teletext system C (NTSC / Intercast) 50Hz Teletext system B ...
Page 35
... The S5D2650 adds an additional output mode and flexibility to vary the modes from line to line. If VBCVBS=0 and VBINSRT=1 S5D2650 will output sliced data on enabled lines. By setting VBIMID to 1, any line for which VBIL=3 will output raw ADC data instead of WSS or CGMS. This mode allows a mixture of sliced and raw data. This can be used to output raw data from a teletext line and sliced data from a closed caption line ...
Page 36
... Sliced Data Output Formats While sliced data is available for many of the output formats, the target application is 656 output format. The description of data format is limited to this mode. The S5D2650 allows this data to be output during active video. Figure 31 shows the timing diagram for VYFMT[1:0]=3. ...
Page 37
... For 16-bit RGB output, truncation with dithering is used to convert the data from 24 bit to 16 bit. 1.9. GAMMA CORRECTION The S5D2650 programmable gamma tables allows the customer to apply many different type of corrections. These corrections can be a standard 2.2 factor for NTSC or 2.8 for PAL. These factors can be applied in the RGB or YUV domains ...
Page 38
... S5D2650 Data Sheet 1.9.1. Programming the S5D2650 The previous response is easily programmed into the S5D2650 loading the 0, 8, 16, 24 etc. values into the GAMMA0,1,2,3 locations. Thus every 8th value is stored. The S5D2650 will use linear interpolation to generate the values between every 8th points. This is shown in the following figure. ...
Page 39
... The flexibility of this architecture is shown in the following example. Here it is assumed that the S5D2650 is operating in a YUV output mode but some form of Gamma correction is required. By converting the RGB gamma correction function back to the YUV color space, the following function can be applied to the U and V signals for improved color performance ...
Page 40
... S5D2650 Data Sheet Figure 34. ELECTRONICS Gamma Correction for Cb and Cr MULTIMEDIA VIDEO PAGE 7/18/03 ...
Page 41
... S5D2650 Data Sheet 1.10. DIGITAL VIDEO OUTPUT The S5D2650 can output digital video data in various formats, which are tabulated in Table 11 Table 11: Digital Video Output Format Clock OFMT 0 YCbCr Type 4:2:2 Pin Cb0 Cr0 C1 Cb1 Cr1 C2 Cb2 Cr2 C3 Cb3 Cr3 C4 Cb4 Cr4 ...
Page 42
... HAV signal. 1.10.1. Validation Code Insertion S5D2650 inserts validation codes during inactive video (HAV is inactive), and invalid video (HAV is active but EHAV is inactive) to assist in recognition of scaled data and VBI data. Table 12 lists the available codes, when they are inserted, and related programming registers. ...
Page 43
... Figure 35. 1.10.2. 656 Op Codes The S5D2650 supports timing synchronization through embedded (656) timing reference codes in the output video data stream. This mode is available for output format 3 ( OFMT[3:0] = 3). The 656 Op Codes follow the CCIR 656 standard. An optional set of 656 Op Codes can be enabled to identify VBI data using the TASKB bit. ...
Page 44
... S5D2650 Data Sheet Fields 60 Hz ODD FIELD 1 525 1 Analog Input 525 524 2 1 Digital output VS VSE=1 VSE=0 VS ODD VSE=1 ODD 656 SAV EAV Codes for VSE=0, VALIGN=1 Y[0.. F1EC B6AB B6AB B6AB B6AB B6AB B6AB 9D80 9D80 9D80 9D80 ...
Page 45
... S5D2650 Data Sheet Fields 50 Hz ODD FIELD 1,3 622 623 624 625 Analog Input 622 623 624 621 Digital Output VS VSE=1 VS VSE=0 ODD VSE=0 ODD 656 SAV EAV Codes for VSE=0, VALIGN=1 Y[0..7] DAC7 DAC7 DAC7 F1EC F1EC TASK B VIP 656 SAV EAV Codes for VSE=0, VALIGN=1, ALT656=1, VBIL15-VBIL1=1, TASKB=1 Y[0 ...
Page 46
... The S5D2650 supports the IIC serial interface for programming the chip registers. 1.11.1. IIC Interface The two wire interface consists of the SCLK and SDAT signals. Data can be written to or read from the S5D2650. For both read and write, each byte is transferred MSB first, and the data bit is valid when the SCLK is high. ...
Page 47
... The second phase also starts with the START signal. It then sends the slave device ID but with the R/W position to indicate data read from the slave device. The host uses the SCLK to shift data out from the S5D2650. A typical second phase in a read transaction is depicted in Figure 40. Auto index increment is supported in Read mode. ...
Page 48
... S5D2650 Data Sheet 2. CONTROL REGISTER DESCRIPTION This section contains information concerning the programmable control registers. Table 14 provides the default power up values for each index, and a bit map for each register. The following pages describe each register in detail and the possible programing values (an * indicates the power-on default). Gamma correction registers are write only ...
Page 49
... S5D2650 Data Sheet Index Mnemonic Default 0x20 VBICTL 00 VBCVBS 0x21 CCDAT1 RO 0x22 CCDAT2 RO 0x23 VBIL30 00 0x24 VBIL74 00 0x25 VBIL118 00 0x26 VBIL1512 00 0x27 TTFRAM 00 0x28 TESTA 00 0x29 UVOFFH 00 TSTCLC 0x2A UVOFFL 33 0x2B UGAIN 00 0x2C VGAIN 00 0x2D VAVB 23 0x2E VAVE 82 0x2F CTRACK 00 0x30 ...
Page 50
... S5D2650 Data Sheet Index Mnemonic bit 7 00h STAT CHIPID CLOCK Status for color lock HLOCK Status for current line tracking mode CDET Status for detection of color PALDET Status for current detected color format. Information contained in this bit is valid only if CLOCK is 1 ...
Page 51
... S5D2650 Data Sheet Index Mnemonic bit 7 01h CMDA POWDN IFMT Manual video input standard select. Standard selection can be controlled automatically if MNFMT=0. 0 Chip is forced to assume input is 50 Hz.* 1 Chip is forced to assume input is 60 Hz. MNFMT Manual input format control override. When this bit is 1 the IFMT bit is enabled. ...
Page 52
... S5D2650 Data Sheet Index Mnemonic bit 7 02h CMDB AGCGN INSEL[2:0] Analog input channel select. 0 AY0 is composite input.* 1 AY1 is composite input. 2 ACR0 is composite input. 3 ACR1 is composite input. 4 AY0 is Luminance input, ACB0 is chrominance input. 5 AY1 is Luminance input, ACB1 is chrominance input. 6 AY0 is luminance input, ACB0 is Cb input, ACR0 is Cr input. ...
Page 53
... S5D2650 Data Sheet Index Mnemonic bit 7 03h CMDC VMEN TSTGEN Enable manual control of horizontal phase and frequency tracking. 0 Auto phase and frequency tracking.* 1 Enable manual control of horizontal phase and frequency with TSTGFR[1:0] and TSTGPH. TSTGFR[1:0] When TSTGEN == 1, these two bits control the horizontal frequency tracking. ...
Page 54
... S5D2650 Data Sheet Index Mnemonic bit 7 04h CMDD EAV GPPORT General purpose port. This register is useful only if DATAA[2: DIRA == 0, this bit is read only and reflects the logic state at PORTA pin. If DIRA == 1, any value written to this bit will appear at PORTA pin. ...
Page 55
... S5D2650 Data Sheet Index Mnemonic bit 7 05h HAVB 0Ch HXTRA HAVB[10:0] This 11-bit register is used to define the start location of the HAV signal relative to the sync tip (for CVBS input, this is the composite video sync tip. For 8-bit CbYCr input, this is the leading edge of the HS1 or EAV). The content of this register is a 2’ ...
Page 56
... S5D2650 Data Sheet Index Mnemonic bit 7 08h HS1E 0Ch HXTRA HS1E[8: HS1 is programmed as an output, this 9-bit register defines the end location of the HS1 HS1BE0 signal. The content of this register is a 2’s complement number which is used as an offset to the default. The resolution for this register clock. ...
Page 57
... S5D2650 Data Sheet Index Mnemonic bit 7 0x0B AGC AGC[7:0] This register is used to manually set AGC when AGCFRZ is set to “1”. The content in the register is unsigned. Index Mnemonic bit 7 0Dh CDEM OUTHIZ CIFCMP[1:0] IF compensation for the chroma path compensation.* 1 Upper chroma side band higher than lower side band. ...
Page 58
... S5D2650 Data Sheet Index Mnemonic bit 7 0Eh PORTAB DIRB DATAA[2:0] Port A data select. For internal gate signal locations. 0 Port A is disconnected from the internal signal path.* 1 Port A is connected to the BPG (back porch gate) signal. 2 Port A is connected to the SYG (sync tip gate) signal. ...
Page 59
... S5D2650 Data Sheet Index Mnemonic bit 7 0x0F LUMA 0 HYPK[1:0] Luminance horizontal peaking control around 3 MHz. 0 Less than nominal peaking.* (0 dB) 1 Nominal peaking. (2 dB) 2 Increased peaking. (4 dB) 3 Maximum peaking. (8 dB) CTRAP Chroma trap (notch filter) in the luma path chroma trap. This mode is recommended for S-video or component video input.* 1 Chroma trap is enabled ...
Page 60
... S5D2650 Data Sheet Index Mnemonic bit 7 0x10 CON CON[7:0] This 8-bit register contains a 2’s compliment number for contrast control. Index Mnemonic bit 7 0x11 BRT BRT[7:0] Brightness control register. The number contained in the register is 2’s compliment. ELECTRONICS Contrast Control bit 6 ...
Page 61
... S5D2650 Data Sheet Index Mnemonic bit 7 0x12 CHROMA ACCFRZ CKILL[1:0] Color kill. 0 Auto detect mode. If color burst is too low or no color burst, chroma data is forced to code 128.* 2 Chroma is always ON. 3 Chroma data is always forced to code 128. CORE[1:0] Chroma data coring coring. ...
Page 62
... S5D2650 Data Sheet Index Mnemonic bit 7 0x13 CHROMB SCHCMP[3:0] Phase constant compare value for color burst phase relative to sync tip. Each step is 22.5 degrees with the value of 0 equal to 0 degree. CDLY[3:0] Chroma path group delay relative to the luma path (in unit of CK delay ...
Page 63
... S5D2650 Data Sheet Index Mnemonic bit 7 0x14 DEMOD FSCDET SECDET CDMLPF CTRACK MNSECAM[1:0] Enable manual SECAM input detection. 0 Detection of SECAM input is automatic.* 2 Force the chip to assume input is not SECAM. 3 Force the chip to assume input is SECAM. MNFSC[1:0] Enable manual Fsc detection. 0 Detection of Fsc frequency is automatic.* 2 Force chip to assume input Fsc is 4 ...
Page 64
... S5D2650 Data Sheet Index Mnemonic bit 7 0x15 SAT SAT[7:0] Color saturation control register. Register content is in 2’s complement if TSTCGN=0. 0 value corresponds to nominal saturation. Index Mnemonic bit 7 0x16 HUE HUE[7:0] Hue control register. The register content is in 2’s compliment format. It covers the range from -180° ...
Page 65
... S5D2650 Data Sheet Index Mnemonic bit 7 0x17 VERTIA MNYCMB VCTRL[2:0] Luminance vertical filter control. 0 Scaler uses LPF path, comb uses HPF.* 1 Scaler uses full bandwidth, comb is disabled. 2 Scaler is disabled, comb uses full bandwidth. 3 Scaler uses LPF, comb is disabled. 4 Scaler is disabled, comb uses HPF. ...
Page 66
... S5D2650 Data Sheet Index Mnemonic bit 7 0x18 VERTIB VSCLEN[1:0] Vertical scaling enable. 0 Vertical scaling is enabled.* 1 Vertical scaling is disabled. 2 Vertical scaling is disabled. Video is 1-line delayed. 3 Vertical scaling is disabled. Video is 2-line delayed. HYDEC Luma path decimation filter enable. 0 Luma path decimation is enabled.* 1 Luma path decimation is disabled. ...
Page 67
... S5D2650 Data Sheet Index Mnemonic bit 7 0x19 VERTIC MNCCMB EVAVOD Enable VAV signal output during ODD field. 0 VAV signal is disabled (always inactive) during ODD field. 1 VAV signal is enabled during ODD field.* EVAVEV Enable VAV signal output during EVEN field. 0 VAV signal is disabled (always inactive) during EVEN field. ...
Page 68
... S5D2650 Data Sheet Index Mnemonic bit 7 0x1A HSCLL 0x1B HSCLH CMBMOD This bit controls when comb is enabled internally. 0 Comb is enabled by the internal signal COMB_EN.* 1 Comb is enabled when VAV is active. HSCL[14:0] The 15-bit register defines a horizontal scaling ratio of HSCL[14:0]/2 value will become effective during the next vertical sync. ...
Page 69
... S5D2650 Data Sheet Index Mnemonic bit 7 0x1E OFMTA GAMEN[1:0] OFMT[3:0] Digital video output format select. 16 and 24 bit data are output at CK2 clock rate. 8 bit data are output at CK clock rate. 0 16-bit YCbCr 4:2:2 output on the Y and C output ports.* 1 12-bit YCbCr 4:1:1 output on the Y and C output ports. ...
Page 70
... S5D2650 Data Sheet Index Mnemonic bit 7 0x1F OFMTB VSVAV EVAVG Gate EVAV with VAV before sending to output. 0 EVAV is not gated with VAV. EVAV may be active outside of active VAV region.* 1 EVAV is gated with VAV. EVAV can be active only when VAV is active. EVEHAV Additional qualifier for EHAV ...
Page 71
... S5D2650 Data Sheet Index Mnemonic bit 7 0x20 VBICTL VBCVBS ODDOS[1:0] Line offset for ODD field. See also VBIL[15:0]. 0 ODD field line offset is -1 compared to EVEN field offset. 2 ODD field line offset is 1 compared to EVEN field. 3 ODD field line offset is 2 compared to EVEN field. ...
Page 72
... S5D2650 Data Sheet First Decoded Close-Caption Data Byte (Read Only) Index Mnemonic bit 7 0x21 CCDAT1 b0 CCDAT1 This byte contains the first byte of the decoded close-caption data as defined in EIA-608. In order for this register to receive the CC data, VBINSRT must be programmed to a “1”, and VYFMT[1:0] must be programmed with the value 3. The same applies to CCDAT2. For normal NTSC Closed Caption decoding, ODDEN should be set to a “ ...
Page 73
... S5D2650 Data Sheet Index Mnemonic bit 7 0x27 TTFRAM TTFRAM[7:0] User programmable Teletext frame alignment pattern. Index Mnemonic bit 7 0x29 UVOFFH TSTCLC TSTCGN 0x2A UVOFFL VOFFST[5:0], These two 6-bit 2’s compliment values are for offset adjustment to the U and V components of UOFFST[5:0] the chroma data. The resolution is 1/4 LSB of the 8-bit U and V. ...
Page 74
... S5D2650 Data Sheet Index Mnemonic bit 7 0x2B UGAIN UGAIN[7:0] U component gain adjustment. The nominal value is 0. Index Mnemonic bit 7 0x2C VGAIN VGAIN[7:0] V component gain adjustment. The nominal value is 0. Index Mnemonic bit 7 0x2D VAVB VAVEV0 The LSB for VAVB and VAVE for the even field. ...
Page 75
... S5D2650 Data Sheet Index Mnemonic bit 7 0x2F CTRACK 0 CFTC[1:0] Chroma frequency tracking time constant. 0 Slower.* 1 Slow. 2 Fast. 3 Faster. CGTC[1:0] Chroma gain tracking time constant. 0 Slower.* 1 Slow. 2 Fast. 3 Faster. DMCTL[1:0] Chroma demodulation bypass mode. 0 Chroma demodulation is enabled.* 1 Chroma demodulation is bypassed for digital YCbCr input. ...
Page 76
... S5D2650 Data Sheet Index Mnemonic bit 7 0x30 POLCTL EVAVPL HS1PL HS1 polarity. 0 Active high.* 1 Active low. VAVPL VAV polarity. 0 Active high.* 1 Active low. HS2PL HS2 polarity. 0 Active high.* 1 Active low.* EHAVPL EHAV polarity. 0 Active high.* 1 Active low. HAVPL HAV polarity. 0 Active high.* 1 Active low ...
Page 77
... S5D2650 Data Sheet Index Mnemonic bit 7 0x31 REFCOD YCRANG YCRANG Digital video output range control and C ranges are limited 254 and B ranges are limited 254 range is limited 235; C range is limited 240 and B ranges are limited 240 ...
Page 78
... S5D2650 Data Sheet Index Mnemonic bit 7 0x35 UNUSEY UNUSEY[7:0] User programmed code to be output for Y data when HAV is inactive. Index Mnemonic bit 7 0x36 UNUSEU UNUSEU[7:0] User programmed code to be output for U data when HAV is inactive. Index Mnemonic bit 7 0x37 UNUSEV UNUSEV[7:0] User programmed code to be output for V data when HAV is inactive ...
Page 79
... Scaler on during VBI interval (defined by VAV).* 1 Scaler off during VBI interval. PERMIN Integration time for auto slice level creation 0 Fast* 1 Slow ELECTRONICS Extra Control Bits for the S5D2650 Version bit 6 bit 5 bit 4 SLEV[1:0] MULTIMEDIA VIDEO bit 3 bit 2 bit 1 OFFST_CONT[1:0] 0 PAGE ...
Page 80
... S5D2650 Data Sheet Index Mnemonic bit 7 0x39 TRACKA STCTRL MAC_DET VCR_DET AGCLSB AGC LSB for control of the 9 bit AGC gain value. This bit only write to AGC when AGCFRZ Write ‘0’ to AGC 9 bit control LSB if AGCFRZ = 1.* 1 Write ‘1’ to AGC 9 bit control LSB if AGCFRZ = 1. ...
Page 81
... S5D2650 Data Sheet Index Mnemonic bit 7 0x3A VBICTLB VBISWAP COFFENB Disable control for the C-path clamp control. 0 C-path clamp works as normal.* 1 C-path clamp disabled. YOFFENB Disable control for the Y-path clamp control.* 0 Y-path clamp works as normal.* 1 Y-path clamp disabled. CC_OVFL Defines when the current CCDAT1,2 data has over written previous data that was not read. ...
Page 82
... S5D2650 Data Sheet Index Mnemonic bit 7 0x3B TRACKB ALT656 AGC_LKG AGC gain tracking loop time constant for initial tracking mode. 0 Same as steady state time constant faster than selected steady state time constant. AGC_LPG AGC gain steady state tracking loop time constant. ...
Page 83
... Polarity control for PAL ID transferred within the RTC data stream. 0 Same polarity as default PID pin.* 1 Inverted polarity. RTC_DTO Enables a DTO reset inside the S5D2650 and sends a DTO reset within the RTC data stream. Function is activated on the rising edge of RTC_DTO. 0 Function disabled.* 1 Function enabled one time when set to 1. ...
Page 84
... S5D2650 Data Sheet Index Mnemonic bit 7 0x3D CMDE ODFST CHIPREVID Four additional bits for determination of current Revision and differentiation from the S5D2650 0 KS0127B C S5D2650 HCORE Luma path horizontal coring. Noise limiter for high frequency portion of luma. 0 Coring function is disabled bit of coring. ...
Page 85
... S5D2650 Data Sheet Index Mnemonic bit 7 0x3E VSDEL TR_MS VSDEL[5:0] When the chip is programmed for digital video input operation, this register provides an offset for the internal line counter to align with input video (VS can be either from the VS pin or from embedded timing code). The register content is unsigned. ...
Page 86
... VIPMODE Allows transfer of hardware sliced VBI data as ancillary data during the following line’s horizontal blanking period. 0 Standard S5D2650 original sliced VBI data transfer.* 1 Optional ancillary sliced VBI data transfer. CTRAPFSC Enable chroma trap location based on Fsc frequency instead of field rate. ...
Page 87
... S5D2650 Data Sheet Index Mnemonic bit 7 0x40 GAMMA0 0x41 GAMMA1 : : : : 0x5F GAMMA31 GAMMA0 Gamma correction base. The desired output for 8*N, where .., 31, is programmed into -GAMMA31 GAMMAN. Note that data written into these addresses are simultaneously written into addresses 0xC0 through 0xDF. ...
Page 88
... S5D2650 Data Sheet Index Mnemonic bit 7 0xC0 GAMUV0 0xC1 GAMUV1 : : : : 0xDF GAMUV31 GAMUV0 U and V gamma correction base. The desired output for 8*N, where .., 31, is -GAMUV31 programmed into GAMUVN. Index Mnemonic bit 7 0xE0 GAMUVD0 - 0xE1 GAMUVD1 - : : : : : : 0xFF GAMUVD31 - GAMUVD0 U and V gamma correction delta. The Nth location of the 32 locations is programmed with a ...
Page 89
... S5D2650 Data Sheet ABSOLUTE MAXIMUM RATINGS Characteristics 3.3-V supply voltage (measured to VSS) 1.8-V supply voltage (measured to VSS) Voltage on any digital pin Ambient operating temperature (case) Storage temperature Junction temperature Vapor phase soldering (1 min.) Notes: 1.Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions ...
Page 90
... S5D2650 Data Sheet ELECTRICAL CHARACTERISTICS Characteristics Supply +3.3V (Analog+I/O Buffer), normal operation +1.8V (Digital Core), normal operation +3V (Analog+I/O Buffer), power down mode +1.8V (Digital Core), power down mode Analog Characteristics Integral linearity error (AGC/ADC only) Differential linearity error (AGC/ADC only) Total harmonic distortion (4 MHz full scale) ...
Page 91
... S5D2650 Data Sheet Characteristics Digital I/O Characteristics Input low voltage Input high voltage Schmitt trigger, negative going threshold (SCLK,SDAT) Schmitt trigger, positive going threshold (SCLK,SDAT) Input low current (V = VSS) IN Input high current(V = VDD) IN Digital output low voltage (I =1~24mA) OL Digital output high voltage (I ...
Page 92
... S5D2650 Data Sheet Characteristics SDAT hold time from rising edge of SCLK Note: AC/DC characteristics provided are per design specifications. Note * case of CVBS Input Mode Note * case of S-Video Input Mode Note * case of Component Input Mode Note * case of Power Down Mode, I2C interface is still alive. ...
Page 93
... S5D2650 Data Sheet CK CK2 Y,C,HAV VAV,HS,VS ODD,PID, EHAV, EVAV Analog Video Input Digital Video Active video Output t dCHIP Figure 42. SDAT t BUF t hSDAT SCLK t hSDA Figure 43. ELECTRONICS t pwhCK t pwhCK2 t Š † f Figure 41. Data Output Blank Active video Analog Video Input to Digital Video Output Delay ...
Page 94
... S5D2650 Data Sheet Application Circuit 1.8V 0.1uF 0.1uF Ω 0.1uF 7 XTALI ...
Page 95
... S5D2650 Data Sheet Package Dimension ELECTRONICS MULTIMEDIA VIDEO PAGE 7/18/03 ...