S5D2650 Samsung Semiconductor, Inc., S5D2650 Datasheet - Page 52

• Manufacturer Part Number: S5D2650
• Description: Multistandard Video Decoder/scaler
• Manufacturer: Samsung Semiconductor, Inc.

S5D2650 Data Sheet
Index
02h
INSEL[2:0]
COMP_PH
AGCFRZ
AGCOVF
VALIGN
AGCGN
Mnemonic
CMDB
ELECTRONICS
Analog input channel select.
0
1
2
3
4
5
6
7
Cb & Cr phase inversion in case of Component input
0
1
Freeze the analog AGC for the Y and C paths at their current values.
0
1
AGC gain control mode.
0
1
VS edge alignment control.
0
1
AGC gain calculation.
0
1
AGCGN
bit 7
AY0 is composite input.*
AY1 is composite input.
ACR0 is composite input.
ACR1 is composite input.
AY0 is Luminance input, ACB0 is chrominance input.
AY1 is Luminance input, ACB1 is chrominance input.
AY0 is luminance input, ACB0 is Cb input, ACR0 is Cr input.
AY1 is luminance input, ACB1 is Cb input, ACR1 is Cr input.
Normal operation *
Phase inversion
AGC is running. Reading AGC register returns the current AGC gain.*
AGC is frozen. Gain can be changed or read with AGC register.
AGC gain tracks to sync tip and back porch delta.
If ADC overflows, AGC gain will be reduced (this has higher priority over normal
sync tip - back porch tracking).*
VS leading edge occurs during serration pulses (typically within the first serration
pulse). VS trailing edge is aligned to half line or beginning of the line depending on
the field.*
VS leading edge is aligned to half line or beginning of the line depending on the
field. VS trailing edge is always aligned to beginning of the line.
Normal mode. AGC gain calculation is based on sync tip to back porch difference
equal to 68 ADC code.*
AGC gain calculation is base on sync tip to back porch difference equal to 54 ADC
code. This will reduce the AGC gain by a factor of 1/1.25 compare to normal mode.
When used in conjunction with PED and RGBH, this effectively increases the input
dynamic range.
VALIGN
bit 6
AGCOVF
Control Register B
bit 5
AGCFRZ COMP_PH
bit 4
bit 3
bit 2
MULTIMEDIA VIDEO
INSEL[2:0]
bit 1
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bit 0
7/18/03