ACS8525 Semtech Corporation, ACS8525 Datasheet - Page 15

• Manufacturer Part Number: ACS8525
• Description: Line Card Protection Switch For Sonet/sdh Systems
• Manufacturer: Semtech Corporation

Figure 5 PLL Block Diagram
The input reference is either passed directly to the PFD or
via a pre-divider (not shown) to produce the reference
input. The feedback 77.76 MHz is either divided or
synthesized to generate the locking frequency.
Any Digital Frequency Synthesis (DFS) generated clock
will inherently have jitter on it equivalent to one period of
the generating clock (pk-pk). The DPLL1 77M Forward
DFS block uses DFS clocked by the 204.8 MHz system
clock to synthesize the 77.76 MHz and, therefore, has an
inherent 4.9 ns of pk-pk jitter. There is an option to use a
feedback APLL (APLL3) to filter out this jitter before the
77.76 MHz is used to generate the feedback locking
frequency in the DPLL1 feedback DFS block. This analog
feedback option allows a lower jitter (<1 ns) feedback
signal to give maximum performance.
The DPLL1 77M Forward DFS block is also the block that
handles Phase Build-out and any phase offset
programmed into the device. Hence, the DPLL1 77M
Forward DFS and the DPLL1 77M Output DFS blocks are
locked in frequency but may be offset in phase.
Revision 3.00/October 2003 © Semtech Corp.
ADVANCED COMMUNICATIONS
DPLL2
Reference
Input
for phase
measurement
only
DPLL1
Reference
Input
DPLL2_meas_
DPLL1_ph
DPLL2
DPLL1
1
0
sts_current_phase
Loop Filter
Loop Filter
PFD and
sts_current_phase
PFD and
Locking
Frequency
Locking
Frequency
8 kHz
DPLL2_meas_
DPLL1_ph
PBO
1
0
Feedback
Forward
Output
77M
77M
DFS
DFS
DFS
DPLL2_frequency
Phase
Offset
Feedback
Forward
DFS
DFS
1
0
0
1
DPLL2_dig_
feedback
DPLL1_frequency
FINAL
Page 15
Output
1
0
DFS
LF
The DPLL1 77M Output DFS block also uses the
204.8 MHz system clock and always generates
77.76 MHz for the output clocks (with inherent 4.9 ns of
jitter). This is fed to DPLL1 LF Output DFS block and to
APLL1. The low frequency DPLL1 LF Output DFS block is
used to produce three frequencies; two of them, Digital1
and Digital2, are available for selection to be produced at
outputs O1 and O2, and the third frequency can produce
multiple E1/DS1 rates via the filtering APLLs. The input
clock to the DPLL1 LF Output DFS block is either
77.76 MHz from APLL1 (post jitter filtering) or 77.76 MHz
direct from the DPLL1 77M Output DFS.
Utilizing the clock from APLL1 will result in lower jitter
outputs from the DPLL1 LF Output DFS block. However,
when the input to the APLL1 is taken from the DPLL1 LF
Output DFS block, the input to that block comes directly
from the DPLL1 77M Output DFS block so that a “loop” is
not created.
APLL1 is for multiplying and filtering. The input to APLL1
can be either 77.76 MHz from the DPLL1 77M Output
DFS block or an alternative frequency from the DPLL1 LF
DPLL1_freq_to_APLL2
DPLL1_frequency
MUX
0
1
0
1
2
1
APLL2
APLL1
APLL3
ACS8525 LC/P
Dividers
Dividers
APLL2
Output
APLL1
Output
Analog
F8525D_017BLOCKDIA_03
DATASHEET
www.semtech.com
01 and 02
01 and 02
FrSync
MFrSync
O1 and O2