ACS8525 Semtech Corporation, ACS8525 Datasheet - Page 39

• Manufacturer Part Number: ACS8525
• Description: Line Card Protection Switch For Sonet/sdh Systems
• Manufacturer: Semtech Corporation

Table 15 Register Map
Revision 3.00/October 2003 © Semtech Corp.
ADVANCED COMMUNICATIONS
RO = Read Only
R/W = Read/Write
chip_id (RO)
chip_revision (RO)
test_register1 (R/W)
test_register2 (R/W)
sts_interrupts (R/W)
sts_current_DPLL_frequency,
see OC/OD
sts_interrupts (R/W)
sts_operating_mode (RO)
sts_priority_table (RO)
sts_current_DPLL_frequency[7:0] 0C 00
sts_sources_valid (RO)
sts_reference_sources (RO)
Alarm Status on inputs:
cnfg_ref_selection_priority (R/W)
cnfg_ref_source_frequency_
<input> (R/W), where <input> =
cnfg_operating_mode (R/W)
force_select_reference_source
(R/W)
cnfg_input_mode (R/W)
cnfg_DPLL2_path (R/W)
cnfg_differential_inputs (R/W)
cnfg_dig_outputs_sonsdh (R/W)
cnfg_digtial_frequencies (R/W)
cnfg_differential_output (R/W)
cnfg_auto_bw_sel
cnfg_nominal_frequency
(R/W)
cnfg_DPLL_freq_limit (R/W) [7:0] 41 76
(RO)
Register Name
SEC1 & SEC2 DIFF 12 22
SEC1 & SEC2 DIFF 1A
SEC1 & SEC2 TTL 11 22
SEC1 & SEC2 TTL
SEC1 DIFF 24 03 divn_SEC1
SEC2 DIFF 25 03 divn_SEC2
SEC1 TTL 22 00 divn_SEC1 TTL lock8k_SEC1
SEC2 TTL 23 00 divn_SEC2 TTL lock8k_SEC2
[18:16] 07 00
[15:8] 0D 00
[15:8] 3D 99
SEC3 14 22
SEC3 1C 04
SEC3 28 03 divn_SEC3
[7:0] 3C 99
00 4D
01 21
02 00
03 14 Phase_alarm
05 FF
06 3F
07 00
08 10 Sync_alarm_
09 01 Sync_alarm
0B 00
0E
0F
19 32
32 00
33 0F
34 CA
35 A0
36 03
38 04
39 08
3A
3B 98 auto_BW_sel
04 12
0A
00
00
00
00
C2
operating_
mode
int
DIFF
DIFF
auto_extsync_
en
7 (MSB)
digital2_frequency
3rd highest priority validated source
programmed_priority_SEC2_DIFF
programmed_priority_SEC2_TTL
Disable_180
DPLL1_main_
ref_failed
DPLL2_Lock
Highest priority validated source
TTL
TTL
lock8k_SEC1
DIFF
lock8k_SEC2
DIFF
lock8k_SEC3
phalarm_
timeout
DPLL2_dig_
feedback
dig2_sonsdh
6
status_SEC2_
DIFF
DPLL1_freq_
soft_alarm
SEC2 DIFF
No Activity
SEC2 TTL
No Activity
SEC2 DIFF
XO_ edge
dig1_sonsdh
FINAL
Page 39
Bucket_id_SEC1 DIFF
Bucket_id_SEC2 DIFF
Bucket_id_SEC1 TTL
Bucket_id_SEC2 TTL
5
digital1_frequency
Bucket_id_SEC3
Bits [15:8] of sts_current_DPLL_frequencyy
Bits [7:0] of sts_current_DPLL_frequency
Bits[15:8] of cnfg_nominal_frequency
Bits[7:0] of cnfg_nominal_frequency
Bits[7:0] of cnfg_DPLL_freq_limit
chip_id[15:8], 8 MSBs of Chip ID
Resync_
analog
status_SEC1_
DIFF
DPLL2_freq_
soft_alarm
SEC1 DIFF
Phase Lock
SEC2 TTL
Phase Lock
SEC2 DIFF
chip_id[7:0], 8 LSBs of Chip ID
4
chip_revision[7:0]
Do not use
Data Bit
Set to 0
status_SEC2_
TTL
SEC2 TTL
extsync_en
DPLL1_lim_int
3
reference_source_frequency_SEC1 DIFF
reference_source_frequency_SEC2 DIFF
reference_source_frequency_SEC1 TTL
reference_source_frequency_SEC2 TTL
2nd highest priority validated source
reference_source_frequency_SEC3
programmed_priority_SEC1_DIFF
programmed_priority_SEC1_TTL
8K Edge
Polarity
status_SEC1_
TTL
Bits [18:16] of sts_current_DPLL_frequency
SEC1 TTL
ip_sonsdhb
programmed_priority_SEC3
Bits [18:16] of sts_current_DPLL_frequency
Currently selected source
forced_select_SEC_input
ACS8525 LC/P
2
DPLL1_operating_mode
DPLL1_operating_mode
Set to 0
No Activity
SEC1 TTL
No Activity
SEC1 DIFF
No Activity
SEC3
SEC2_DIFF_
PECL
Output O1 _LVDS_PECL
1
DATASHEET
www.semtech.com
Set to 0
status_SEC3
SEC3
Phase Lock
SEC1 TTL
Phase Lock
SEC1 DIFF
Phase Lock
SEC3
reversion_
mode
SEC1_DIFF_
PECL
0 (LSB)