ACS8525 Semtech Corporation, ACS8525 Datasheet - Page 67

• Manufacturer Part Number: ACS8525
• Description: Line Card Protection Switch For Sonet/sdh Systems
• Manufacturer: Semtech Corporation

Address (hex):
Revision 3.00/October 2003 © Semtech Corp.
ADVANCED COMMUNICATIONS
Register Name
Bit No.
Bit 7
7
6
5
4
3
48
cnfg_monitors
los_flag_on_
TDO
Description
Not used.
los_flag_on_TDO
Bit to select whether the main_ref_fail interrupt
from DPLL1 is flagged on the TDO pin. If enabled
this will not strictly conform to the IEEE 1149.1 JTAG
standard for the function of the TDO pin. When
enabled the TDO pin will simply mimic the state of
the main_ref_fail interrupt status bit.
ultra_fast_switch
Bit to enable ultra-fast switching mode. When in this
mode, the device will disqualify a locked-to source
as soon as it detects a few missing input cycles.
ext_switch
Bit to enable external switching mode. When in
external switching mode, the device is only allowed
to lock to a pair of sources. If the programmed
priority of input SEC1 TTL is non-zero, then when the
SRCSW pin is High, the device will be forced to lock
to input SEC1 TTL regardless of the signal present
on that input. If the programmed priority of input
SEC1 TTL is zero, then it will be forced to lock to
input SEC1 DIFF instead. If the programmed priority
of input SEC2 TTL is non-zero, then when the
SRCSW pin is Low, the device will be forced to lock
to input SEC2 TTL regardless of the signal present
on that input. If the programmed priority of input
SEC2 TTL is zero, then it will be forced to lock to
input SEC2 DIFF instead.
* The default value of this bit is dependent on the
value of the SRCSW pin at power-up.
PBO_freeze
Bit to control the freezing of Phase Build-out
operation. If Phase Build-out has been enabled and
there have been some source switches, then the
input-output phase relationship of DPLL1 is
unknown. If Phase Build-out is no longer required,
then it can be frozen. This will maintain the current
input-output phase relationship, but not allow
further Phase Build-out events to take place. Simply
disabling Phase Build-out could cause a phase shift
in the output, as DPLL1 re-locks the phase to zero
degrees.
Bit 6
ultra_fast_
switch
Bit 5
Description
ext_switch
Bit 4
FINAL
Page 67
(R/W) Configuration register
controlling several input
monitoring and switching options.
PBO_freeze
Bit Value
Bit 3
0
1
0
1
0
1
0
1
-
PBO_en
Value Description
-
Normal mode, TDO complies with IEEE 1149.1.
TDO pin used to indicate the state of the
main_ref_fail interrupt status. This allows a system
to have a hardware indication of a source failure
very rapidly.
Currently selected source only disqualified by Leaky
Bucket or frequency monitors.
Currently selected source disqualified after less
than 3 missing input cycles.
Normal operation mode.
External source switching mode enabled. Operating
mode of the device is always forced to be “locked”
when in this mode.
Phase Build-out not frozen.
Phase Build-out frozen, no further Phase Build-out
events will occur.
Bit 2
Default Value
ACS8525 LC/P
Bit 1
DATASHEET
www.semtech.com
0000 0100*
Bit 0