ACS8525 Semtech Corporation, ACS8525 Datasheet - Page 6

• Manufacturer Part Number: ACS8525
• Description: Line Card Protection Switch For Sonet/sdh Systems
• Manufacturer: Semtech Corporation

Table 3 Other Pins (cont...)
Revision 3.00/October 2003 © Semtech Corp.
ADVANCED COMMUNICATIONS
17
18
19,
20
23,
24
25,
26
28
29
30
33
34
35
37
41
42
43
44
47
48
49
50
51
52
56
64
Pin Number
FrSync
MFrSync
O1POS,
O1NEG
SEC1_POS,
SEC1_NEG
SEC2_POS,
SEC2_NEG
SYNC1
SEC1
SEC2
SYNC2
SEC3
SYNC3
TRST
TMS
CLKE
SDI
CSB
SCLK
PORB
TCK
TDO
TDI
SDO
O2
SONSDHB
Symbol
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
LVDS/PECL
PECL/LVDS
PECL/LVDS
TTL/CMOS
TTL/CMOS
TTL/CMOS
TTL/CMOS
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
D
D
D
D
D
D
D
D
D
D
U
D
U
D
D
D
D
FINAL
Page 6
Output Reference: 8 kHz Frame Sync output.
Output Reference: 2 kHz Multi-Frame Sync output.
Output Reference: Programmable, default 38.88 MHz, LVDS.
Input Reference: Programmable, default 19.44 MHz, PECL.
Input Reference: Programmable, default 19.44 MHz PECL.
(Master) Multi-Frame Sync 2kHz Input: Connect to 2 or 8 kHz
Multi-Frame Sync output of Master SETS.
(Master) Input Reference: Programmable, default 8 kHz.
(Slave) Input Reference: Programmable, default 8 kHz.
(Slave) Multi-Frame Sync 2 kHz: Connect to 2 or 8 kHz Multi-Frame Sync
output of Slave SETS.
(Stand-by) Input Reference: External stand-by reference clock source,
programmable, default 19.44MHz.
(Stand-by) Input Reference: External stand-by 2 or 8 kHz Multi-Frame
Sync clock source.
JTAG Control Reset Input: TRST = 1 to enable JTAG Boundary Scan
mode. TRST = 0 is Boundary Scan stand-by mode, still allowing normal
device operation (JTAG logic transparent). NC if not used.
JTAG Test Mode Select: Boundary Scan enable. Sampled on rising edge
of TCK. NC if not used.
SCLK Edge Select: SCLK active edge select, CLKE = 1, selects falling
edge of SCLK to be active.
Serial Interface Address: Serial Data Input.
Chip Select (Active Low): This pin is asserted Low by the microprocessor
to enable the microprocessor interface.
Serial Data Clock. When this pin goes High data is latched from SDI pin.
Power-On Reset: Master reset. If PORB is forced Low, all internal states
are reset back to default values.
JTAG Clock: Boundary Scan clock input.
JTAG Output: Serial test data output. Updated on falling edge of TCK.
JTAG Input: Serial test data Input. Sampled on rising edge of TCK.
Interface Address: SPI compatible Serial Data Output.
Output Reference: Programmable, default 19.44 MHz.
SONET or SDH Frequency Select: Sets the initial power-up state (or
state after a PORB) of the SONET/SDH frequency selection registers,
Reg. 34, Bit 2 and Reg. 38, Bit 5, Bit 6 and Reg. 64 Bit 4. When set Low,
SDH rates are selected (2.048 MHz etc.) and when set High, SONET
rates are selected (1.544 MHz etc.) The register states can be changed
after power-up by software.
Description
ACS8525 LC/P
DATASHEET
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