ACS8946 Semtech Corporation, ACS8946 Datasheet - Page 10

• Manufacturer Part Number: ACS8946
• Description: Jitter Attenuating, Multiplying Phase Locked Loop, with Protection Switch, for Oc-12/stm-4 and GbE
• Manufacturer: Semtech Corporation

Jitter Filtering: Partnering with Semtech
Line Card Protection Parts
One possible line card solution is to use the ACS8946 on
the line card to provide line card protection and direct
jitter filtering of references received from a Semtech SETS
device (ACS8520/30) on the sync card. If a Semtech LC/P
part (ACS8525) is used on the line card, another possible
solution uses the ACS8946 after the Semtech LC/P part
to dejitter the LC/P device’s output.
In the first solution, Master/Slave phase alignment on
reference switchover is taken care of by a redundant pair
arrangement of SETS devices, which use their output
phase alignment features to ensure the ACS8946 is
supplied with input clocks that are very closely tied in
phase. Then, on a line card reference switch, the
ACS8946 acts as a simple MUX adding negligible phase
offset between the references, giving very low output
disturbance for the combined system, as well as
performing its dejittering function.
In the second, more sophisticated solution, the reference
switching capability of ACS8946 is not used, as this is
carried out by the SETS or LC/P part.
In both cases, the ACS8946 can be used as both an
output jitter cleaner, and as a rate converter (19.44 MHz
and above).
One “Real World” application for the ACS8946 is to use it
to dejitter the 19.44 MHz output from a Semtech
ACS8525 LC/P device. In this case it is recommended to
set the ACS8946 PLL bandwidth to around 2 kHz to
provide a low jitter total solution. The test results detailed
in the Electrical Specifications section show the “Real
World” performance of this combination of parts which is
a superior solution to those traditionally using simple
discrete PLLs, and has the following advantages:
Revision 3/November 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
Typical final output jitter. e.g. 2.8 ps rms measured
over the integration range of 12 kHz -20 MHz offset
from carrier.
Low overall bandwidth, 18 Hz for example—dictated
by the ACS8525.
High input jitter attenuation and roll-off:
First, second and third order roll-off points:
• - 20 dB/decade 18 Hz to 2 kHz,
• - 40 dB/decade 2 kHz to 200 kHz and
• - 60 dB/decade for >200 kHz.
FINAL
Page 10
Input Jitter Tolerance
Jitter tolerance is defined as the maximum amplitude of
sinusoidal jitter that can exist on the input reference clock
above which the device fails to acquire/maintain lock.
For the stand-alone device, the jitter tolerance is shown in
Figure 4. for an undivided reference i.e. full rate PFD. For
frequencies below the PLL bandwidth, jitter tolerance is
seen to decrease at a rate of -20 dB per decade. For jitter
frequencies above the PLL bandwidth, jitter tolerance is
limited to 0.9 UI p-p.
Note...If the reference clock is divided, then the jitter tolerance
will be improved.
When the ACS8946 follows an ACS8525, the input jitter
tolerance is wholly defined by the ACS8525. The system
jitter tolerance is dramatically increased due to the
extended phase capture range of the digital PLL within the
ACS8525.
Figure 4 Jitter Tolerance ACS8946
Jitter Transfer
Jitter transfer is a ratio of input jitter present on the
reference clock to the filtered jitter present on the output
clock. Standalone, the ACS8946 Jitter Transfer
1000
Typical final output jitter, e.g. 2.9 ps rms (measured
over the integration range 12 kHz - 20 MHz) dictated
by the ACS8946.
High frequency stability when all input clocks fail;
holdover frequency control to Stratum 3—dictated by
the ACS8525.
0.01
100
0.1
10
1
10
100
Input Jitter Tolerance With 2kHz PLL Bandwidth
Jitter Frequency Offset from Carrier (Hz)
1000
ACS8946 JAM PLL
10000
100000
DATASHEET
www.semtech.com
1000000
ACS8946 Jitter
Tolerance
OC_12
Tolerance Mask
OC_48
Tolerance Mask