ACS8946 Semtech Corporation, ACS8946 Datasheet - Page 21

• Manufacturer Part Number: ACS8946
• Description: Jitter Attenuating, Multiplying Phase Locked Loop, with Protection Switch, for Oc-12/stm-4 and GbE
• Manufacturer: Semtech Corporation

Table 15 Output Configuration and Selection for Ethernet Rates (156.25 MHz or 125 MHz input) (cont...)
Output Jitter
The output jitter meets all requirements of ITU, Telcordia
and ETSI standards for SONET rates up to 622.08 MHz
(OC-12/STM-4). See the “Electrical Specifications”
sections for details on the jitter figures across the
different output jitter frequency bands relevant to each
specification.
The recommended bandwidth of around 2 kHz is suitable
for both meeting the specification on output jitter
generation requirements and for filtering out the input
jitter from the input clock.
System Reset
After power-up or a system reset via the RESETB (pin 40),
the internal control logic waits for the presence of an input
signal of approximately the correct frequency (at least
40% of the nominal) and then allows a further settling
time of 60 ms before allowing internal frequency tuning,
frequency-locking and phase-locking on to the input clock.
Consequently reset should be removed only when the
input frequency is within 400 ppm of the nominal
frequency.
Revision 3/November 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
Row no.
23
24
25
26
27
28
29
30
31
32
33
34
Note: (i) Odd divider = 5 (see Table 13)
ALARM2_CO1
CFG_OUT2
CFG_OUT2
CFG_OUT2
CFG_OUT2
CFG_OUT2
CFG_OUT2
ALARMC_CO3
ALARMC_CO3
ALARMC_CO3
ALARMC_CO3
ALARMC_CO3
CFG_IN0
Wiring of Configuration Pins
ALARMC_CO3
GND
VDD
ALARM1_CO0
ALARM2_CO1
CFG_OUT2
ALARMC_CO3
GND
VDD
ALARM1_CO0
ALARM2_CO1
CFG_OUT2
CFG_IN1
62.50
62.50
62.50
62.50
62.50
62.50
62.50
31.25
31.25
31.25
31.25
15.63
FINAL
Page 21
AB = 11
Layout Recommendations
It is highly recommended to use a stable and filtered 3.3 V
power supply to the device. A separate filtered power and
ground plane is recommended with supply decoupling
capacitors of 10 nF and 100 pF utilizing good high
frequency chip capacitors (0402 or 0603 format surface-
mount package) on each VDD. Good differential signal
layout on the input and output lines should be used to
ensure matched track impedance and phase. Contact
Semtech directly for further layout recommendations.
“Available Rates” and Associated “AB” Values (See Note (i))
31.25
31.25
31.25
15.63
15.63
15.63
7.81
15.63
15.63
15.63
7.81
7.81
AB = 10
ACS8946 JAM PLL
7.81
7.81
3.91
7.81
7.81
3.91
3.91
7.81
7.81
3.91
3.91
3.91
AB = 01
DATASHEET
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3.91
Off
Off
3.91
Off
Off
Off
3.91
Off
Off
Off
Off
AB = 00