ACS8946 Semtech Corporation, ACS8946 Datasheet - Page 27

• Manufacturer Part Number: ACS8946
• Description: Jitter Attenuating, Multiplying Phase Locked Loop, with Protection Switch, for Oc-12/stm-4 and GbE
• Manufacturer: Semtech Corporation

Table 22 DC Characteristics: CML Output Port
Table 23 DC Characteristics: LVPECL Output Port
Note: (i) With a 50 ohms load on each pin to V
Table 24 DC Characteristics: LVTTL/CMOS Output Port
Input and Output Interface Terminations
Interfacing to either the same type or electrically different
interface types is illustrated by the following circuit
diagrams in Figures 14 to 19.
In applications where the output clocks are always
running, they may be A.C. coupled, allowing the receive
end to be at any common mode voltage, however, the
lines must always be terminated at their characteristic
impedance.
The preferred termination for the CML type output is 50 Ω
to VDD, as shown in Figure 14. A.C. coupling may be used
subsequently to translate the levels to other interface
types, e.g. to LVPECL/LVDS as shown in Figure 15.
The example of Figure 17 shows LVPECL to LVPECL
terminations with D.C. coupling, so that the ACS8946
sees an equivalent load of around 50 Ω from the resistor
Revision 3/November 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
I
Single-ended output voltage amplitude with 50Ω load
to V
Differential output voltage amplitude with 50Ω load
to VDD and 50Ω input impedance into next stage on
both pins.
LVPECL Output Low Voltage (Note (i))
LVPECL Output High Voltage (Note (i))
LVPECL Output Differential Voltage (Note (i))
Output Low Voltage @ I
Output High Voltage @ I
Low Level Output Current @ V
High Level Output Current @ V
OUT
DD
current source
and 50Ω input impedance into next stage.
Parameter
Parameter
Parameter
OL
OH
(MAX)
(MIN)
OL
OH
= 0.4 V
= 2.4 V
DD
-2V
V
V
V
OH_LVPECL
OD_LVPECL
OL_LVPECL
Symbol
Symbol
Symbol
I
V
V
V
V
I
I
OUT
OH
OL
OD
OH
OS
OL
FINAL
Page 27
arrangement at the receiver end. Note that signal levels
given in the accompanying graph are nominal levels at
622.08 MHz, and will change with load.
The preferred termination circuitry for the LVDS signals
between the ACS8525/26/27 and the ACS8946 LVPECL
is shown in Figure 19. The bias for the LVPECL input is set
for A.C. inputs at a mid point of approximately 2 V (with a
3.3 V VDD), as opposed to a normal D.C. coupled bias of
VDD - 2 V. This is due to the push-pull nature of an A.C.
coupled signal.
Note: Where inputs to the ACS8946 are AC coupled,
problems may be experienced with activity detection. This
is due to noise/cross-talk on the inputs being interpreted
as activity. To avoid this, DC couple wherever possible and
if AC coupling must be used, consider offsetting the DC
bias of the N and P signals, see Figure 16.
Minimum
Minimum
Minimum
V
V
DD
DD
0.37
13.3
2.4
-1.45
2
2
-
-
-
-2.1
Typical
Typical
Typical
400
800
16
-
-
-
-
-
-
-
ACS8946 JAM PLL
Maximum
Maximum
Maximum
V
V
DD
DD
1.22
19.2
0.4
-1.62
-0.88
-
-
-
-
-
DATASHEET
www.semtech.com
Units
Units
Units
mA
mV
mV
mA
mA
V
V
V
V
V