ACS8946 Semtech Corporation, ACS8946 Datasheet - Page 13

• Manufacturer Part Number: ACS8946
• Description: Jitter Attenuating, Multiplying Phase Locked Loop, with Protection Switch, for Oc-12/stm-4 and GbE
• Manufacturer: Semtech Corporation

Table 9 156.25 MHz Input Frequency
Source Switching - State Diagram
Figure 11 Simplified State Diagram of Source Switching
The state diagram in Figure 11 shows a simplified view of
the automatic switching behavior in the presence of
activity alarms. The ALARMC_CO3 signal from the PFD is
used to disqualify a clock, and the signals ALARM1_CO0
and ALARM2_CO1 representing no activity on input
clocks CLK1 and CLK2 respectively, are used to
determine whether or not to select the remaining clock.
Switching between CLK1 and CLK2 is non-revertive.
With ALARMC_CO3 providing a view of the currently
selected clock that is independent to ALARM1_CO0 and
ALARM2_CO1 signals, source selection behavior can be
more complex when these alarm signals disagree, and so
the state machine is necessarily more complex than the
one shown here in order to accommodate such behavior
e.g. when a clock signal is disconnected for a very short
period of time, or when an input clock is running at the
wrong frequency. If further details are required contact
Semtech Sales Support.
Configuration
A higher degree of flexibility and programmability is
possible via the use of configuration pins on the device.
Permanent connections made externally from
CFG_IN[7:0] pins to the configuration output pins
ALARM1_CO0, ALARM2_CO1, CFG_OUT2, ALARMC_CO3
or to ground or VDD set up the device.
Revision 3/November 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
2000
4000
8000
ALARM SIGNALS:
ALARMC_CO3 -- Activity alarm for the currently selected clock (from PFD)
ALARM1_CO0 -- Activity alarm for CLK1
ALARM2_CO1 -- Activity alarm for CLK2
Closed Loop
Bandwidth
CLK 1
75
150
270
R1 & R2/
Ω
ALARMC_CO3 = 1
ALARM1_CO0 = 0
ALARMC_CO3 = 1
ALARM2_CO1 = 0
15
4.7
0.68
C2 & C4/
µF
F8946D_012SimpStateDiag_01
CLK 2
100
33
7.5
C1 & C3
µF
FINAL
Page 13
The ACS8946 GUI software presents the configuration
information in the most user-friendly manner, though the
following tables can be used instead to work out the
connectivity required for a particular configuration. For
example, the last five columns in Table 10 give the results
of the wired connections shown in the second and third
columns. E.g., taking the row 7, connecting pin CFG_IN2
to VDD and CFG_IN3 to ALARM2_C01, gives an input
frequency of 19.44 MHz, a highest output frequency of
622.08 MHz and configures the outputs as LVPECL.
Output Configuration
The output spot frequency selection for OUT1 is
asynchronously controlled by the RATE1A/B select pins
(pins 47 and 48), which select one from a set of four
“Available Rates” that have been pre-selected at power-
up by the wiring configuration of pins 18 and 19
(CFG_IN[1:0]). The wiring configuration of these two pins
preselects a set of any four out of seven rates:
19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz,
311.04 MHz, 622.08 MHz and disabled, which means
that each of the four outputs can run independently at any
one of the four pre-selected rates - chosen by the AB value
in Table 11 and odd divisions thereof as defined by the
start-up configuration of CFG_IN2/CFG_IN3 and/or
CFG_IN6/CFG-IN7 respectively).
OUT2 is asynchronously controlled by the RATE2A/B
select pins (pins 45 and 46) in the same way as OUT1.
Outputs OUT3 and OUT4 cannot be controlled
asynchronously; the output frequency selection is
controlled at power-up or on reset by a combination of the
connections of CFG_IN[1:0] and CFG_IN[5:4] to either
VSS, VDD, ALARM1_CO0 (pin 13) or ALARM2_CO1 (pin
14). Given the four Available Rates have been configured
as described previously, which one of these four rates is
available on OUT3 is then dependent on the connections
of the CFG_IN4 and CFG_IN5 pins to either VSS, VDD,
ALARM1_CO0 (pin 13) or ALARM2_CO1 (pin 14)—see
Table 12.
The method to configure the device is summarized as
follows:
Select the required “Available Rates” that will be
made available for selection at all four outputs using
CFG_IN[1:0] (See Table 11).
Define the frequencies of the fixed outputs
OUT3/OUT4 using CFG_IN[5:4] (See Table 12) and
the required RESYNC Edge result.
ACS8946 JAM PLL
DATASHEET
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