ACS8946 Semtech Corporation, ACS8946 Datasheet - Page 4

• Manufacturer Part Number: ACS8946
• Description: Jitter Attenuating, Multiplying Phase Locked Loop, with Protection Switch, for Oc-12/stm-4 and GbE
• Manufacturer: Semtech Corporation

Table 2 Internally Connected (IC) Pin
Table 3 Functional Pins
Revision 3/November 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
37
2
3
5
6
8
9
11
12
13
14
Pin No.
Pin No.
IC1
OUT1N
OUT1P
OUT2N
OUT2P
OUT3N
OUT3P
OUT4N
OUT4P
ALARM1_CO0
ALARM2_CO1
Symbol
Symbol
I/O
I/O
O
O
O
O
O
O
O
O
O
O
-
LVCMOS
LVCMOS
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
CML or
CML or
CML or
CML or
CML or
CML or
LVTTL/
LVTTL/
CML or
CML or
Type
Type
-
Internally Connected: Connect to ground.
One of four CML or LVPECL differential outputs, partnered with pin 3; programmable at
spot frequencies from 19.44 MHz up to 625.00 MHz. For outputs OUT1 and OUT2 only,
output frequency can be instantly configured using Rate Selection pins (pins 47 and 48
for OUT1), from a set of four pre-configured “Available Rates”. See“Configuration” on
page 13. Output is on when VDD01 is supplied with 3.3 V, or off when VDD01 is tied to
zero volts. If VDD01 is connected to 0 V remove external biasing resistors.
CML or LVPECL differential output partnered with pin 2. See pin 2 description for more
detail.
One of four CML or LVPECL differential outputs, partnered with pin 6; programmable at
spot frequencies from 19.44 MHz up to 625.00 MHz. For outputs OUT1 and OUT2 only,
output frequency can be instantly configured using Rate Selection pins (pins 45 and 46
for OUT2), from a set of four pre-configured “Available Rates”. See“Configuration” on
page 13. Output is on when VDD02 is supplied with 3.3 V, or off when VDD02 is tied to
zero volts. If VDD02 is connected to 0 V remove external biasing resistors.
CML or LVPECL differential output partnered with pin 5. See pin 5 description for more
detail.
One of four CML or LVPECL differential outputs, partnered with pin 9; programmable at
spot frequencies from 19.44 MHz up to 625.00 MHz. For outputs OUT3 and OUT4 only,
the output frequency selection is controlled at power-up or on reset from a set of four
pre-configured “Available Rates”. See“Configuration” on page 13. Output is on when
VDD03 is supplied with 3.3 V, or off when VDD03 is tied to zero volts. If VDD03 is
connected to 0 V remove external biasing resistors.
CML or LVPECL differential output partnered with pin 8. See pin 8 description for more
detail.
One of four CML or LVPECL differential outputs, partnered with pin 12; programmable at
spot frequencies from 19.44 MHz up to 625.00 MHz. For outputs OUT3 and OUT4 only,
the output frequency selection is controlled at power-up or on reset from a set of four
pre-configured “Available Rates”. See“Configuration” on page 13. Output is on when
VDD04 is supplied with 3.3 V, or off when VDD04 is tied to zero volts. If VDD04 is
connected to 0 V remove external biasing resistors.
CML or LVPECL differential output partnered with pin 11. See pin 11 description for more
detail.
Activity alarm output for the CLK1P/CLK1N input reference clock. Active high; high
indicating clock failure. It is also used to configure the device at power-up, where it is
used as a configuration output pin, that may be connected to CFG_IN[0:7] input pins as
required. See “Configuration” on page 13.
Activity alarm output for the CLK2P/CLK2N input reference clock. Active high; high
indicating clock failure. It is also used to configure the device at power-up time, where it
is used as a configuration output pin, that may be connected to CFG_IN[0:7] input pins
as required. See “Configuration” on page 13.
FINAL
Page 4
Description
Description
ACS8946 JAM PLL
DATASHEET
www.semtech.com