ACS8509 Semtech Corporation, ACS8509 Datasheet - Page 29

• Manufacturer Part Number: ACS8509
• Description: Synchronous Equipment Timing Source for Sonet or SDH Network Elements
• Manufacturer: Semtech Corporation

Table 14 Register Description (cont...)
Revision 2.00/January 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
34
Addr.
(Hex)
cnfg_mode
Register Name
This register contains several individual configuration fields, as detailed below:
Bit 7
=1 Auto 2 kHz Sync enable: External 2 kHz Sync will be enabled only when the source
is locked to 6.48 MHz. Otherwise it will be disabled (default)
=0 Auto 2 kHz Sync disable: The user controls this function using bit 3 of this register,
as described below.
Bit 6
=1 Phase Alarm Timeout enable: The phase alarm will timeout after 100 seconds
(default).
=0 Phase Alarm Timeout disable: The phase alarm will not timeout and must be reset
by software.
Bit 5
=1 Rising Clock Edge selected: The device will reference to the rising edge of the
external 12.8 MHz crystal oscillator signal
=0 Falling edge Edge selected: The device will reference to the falling edge of the
external 12.8 MHz crystal oscillator signal (default).
Bit 4
=1 Holdover offset enable: The device will adopt the Holdover offset value stored in
the cnfg_holdover_offset register, in order to set the frequency in Holdover
=0 Holdover offset disable: The device will ignore the value and Holdover will freeze
the frequency of the DPLL on entering Holdover mode (default).
Bit 3
= 1 External 2 kHz Sync Enable: The device will align the phase of its internally
generated Frame Sync signal (8 kHz) and Multi-Frame Sync signal (2 kHz) with that of
the signal supplied to the Sync2K pin. The device should be locked to a 6.48 MHz
output from another ACS8509.
= 0 External 2 kHz Sync Disable: The device will ignore the Sync2k pin.
Bit 2
= 1 SONET Mode: The device expects the input frequency of any input channel given
the value '0001' in the cnfg_ref_source_frequency register to be 1544 kHz
= 0 SDH Mode: The device expects the input frequency of any input channel given the
value “0001” in the cnfg_ref_source_frequency register to be 2048 kHz.
At start-up or reset the bit value will be defaulted to the setting of pin SONSDHB. This
setting can subsequently be altered by changing this bit value.
Bit 1
= 1 Master Mode: The device will adopt the master mode and make the active
decisions of which source to select, etc. This bit is writeable, but its default value is
determined by the pin, MSTSLVB.
= 0 Slave Mode: The device will adopt the slave mode and will follow the master
device.
At start-up or reset the bit value will be defaulted to the setting of pin MSTSLVB. This
setting can subsequently be altered by changing this bit value.
Bit 0
= 1 Revertive Mode: The device will switch to the highest priority source available
shown in the sts_priority_table register, bits (7:4)
= 0 Non Revertive Mode: The device will retain the presently selected source
(default).
FINAL
Page 29
Description
ACS8509 SETS
Default Value (Bin)
DATASHEET
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(SONSDHB=0)
(SONSDHB=1)
(SONSDHB=0)
(SONSDHB=1)
(MSTSLVB=0)
(MSTSLVB=0)
(MSTSLVB=1)
(MSTSLVB=1)
11001000
11001100
11000010
11000110