ACS8509 Semtech Corporation, ACS8509 Datasheet - Page 43

• Manufacturer Part Number: ACS8509
• Description: Synchronous Equipment Timing Source for Sonet or SDH Network Elements
• Manufacturer: Semtech Corporation

JTAG
The JTAG connections on the
boundary scan to be made. The JTAG implementation is
fully compliant to IEEE 1149.1, with the following minor
exceptions, and the user should refer to the standard for
further information.
1. The output boundary scan cells do not capture data
from the core, and so do not support INTEST. However this
does not affect board testing.
2. In common with some other manufacturers, pin TRST is
internally pulled low to disable JTAG by default. The
standard is to pull high. The polarity of TRST is as the
standard: TRST high to enable JTAG boundary scan mode,
TRST low for normal operation.
Table 15 Master-Slave Relationship
Notes: (i) Both ACS8509 must build a common priority table so that the Slave ACS8509 can select the same input reference source as the
Revision 2.00/January 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
All good
Some Failed
Good
Good
Good
Failed
Failed
Failed
Failed
Master ACS8509
Ref_sources to
(iii) Slave ACS8509 outputs must remain in phase with those of Master ACS8509.
(ii) Slave ACS8509 uses common priority table, built before Master ACS8509 failed - priority table can be modified asstatus of the
Master ACS8509 if the Master fails (when the Master is OK, the Slave locks to the Master's output).
input reference sources changes.
All good
Some others failed Good
Good
Good
Good
Failed
Failed
Failed
Failed
Slave ACS8509
Ref_sources to
ACS8509
Good
Good
Failed
Failed
Failed
Good
Failed
Failed
Master ACS8509
allow a full
Status
Good
Failed
Failed
Good
Failed
Good
Good
Good
Failed
Slave ACS8509
FINAL
Page 43
Status
3. The device does not support the optional tri-state
capability (HIGHZ). This will be supported on the next
revision of the device.
The JTAG timing diagram is shown in Figure 13.
PORB
The Power On Reset (PORB) pin resets the device if forced
Low for a power on reset to be initiated. The reset is
asynchronous, the minimum Low pulse width is 5 ns.
Reset is needed to initialize all of the register values to
their defaults. Asserting Reset is required at power on,
and may be re-asserted at any time to restore defaults.
This is implemented most simplistically by an external
capacitor to GND along with the internal pull-up resistor.
The ACS8509 is held in a reset state for 250 ms after the
PORB pin has been pulled High. In normal operation PORB
should be held High.
Locked (ref_x)
Dead
Dead
Locked (ref_y)
Locked (ref_x)
Dead
Dead
Holdover
Holdover
Master ACS8509
Locked to Master
Locked to Master
Dead
Locked to Master
Dead
Holdover
Dead
Locked (ref_x)
Dead
Slave ACS8509
ACS8509 SETS
Output
DATASHEET
Note (i)
Note (i)
Note (ii)
Note (iii)
www.semtech.com
Comments