ACS8509 Semtech Corporation, ACS8509 Datasheet - Page 37

• Manufacturer Part Number: ACS8509
• Description: Synchronous Equipment Timing Source for Sonet or SDH Network Elements
• Manufacturer: Semtech Corporation

The input port <SEC3> is for the connection of the
synchronous clock of the T
device (or the active-Slave device), to be used to align the
T
this device is acting in a subordinate-Slave or
subordinate-Master role.
Ultra Fast Switching
A reference source is normally disqualified after the leaky
bucket monitor thresholds have been crossed. An option
for a faster disqualification has been implemented,
whereby if register 48H, bit 5 (Ultra Fast Switching), is set
then a loss of activity of just a few reference clock cycles
will set the “no activity alarm” and cause a reference
switch. This can be chosen to cause an interrupt to occur
instead of or as well as causing the reference switch. The
sts_interrupts register 05 Hex Bit 14 (main_ref_failed) of
the interrupt status register is used to flag inactivity on the
reference that the device is locked to much faster than
the activity monitors can support. If bit 6 of the
cnfg_monitors register (flag ref loss on TDO) is set, then
the state of this bit is driven onto the TDO pin of the
device.
The flagging of the loss of the main reference failure on
TDO is simply allowing the status of the sts_interrupt bit
14 to be reflected in the state of the TDO output pin. The
pin will, therefore remain High until the interrupt is
cleared. This functionality is not enabled by default so the
usual JTAG functions can be used. When JTAG is normally
used straight out of power-up, then this feature will have
no bearing on the functionality. The TDO flagging feature
will need to be disabled if JTAG is not enabled on power-
up and the feature has since been enabled.
When the TDO output from the ACS8509 is connected to
the TDI pin of the next device in the JTAG scan chain, the
implementation should be such that a logic change
caused by the action of the interrupt on the TDI input
should not effect the operation when JTAG is not active.
Clock Quality Monitoring
Clock quality is monitored and used to modify the priority
tables of the local and remote ACS8509 devices. The
following parameters are monitored:
Revision 2.00/January 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
OUT0
output with the Master (or active-Slave) device if
OUT0
output of the Master
FINAL
Page 37
1. Activity (toggling)
2. Frequency (This monitoring is only performed when
there is no irregular operation of the clock or loss of clock
condition)
Any reference source which suffers a loss-of-signal, loss-
of-activity, loss-of-regularity or clock out-of-band condition
will be declared as unavailable.
Clock quality monitoring is a continuous process which is
used to identify clock problems. There is a difference in
dynamics between the selected clock and the other
reference clocks. Anomalies occurring on non-selected
reference sources affect only that source's suitability for
selection, whereas anomalies occurring on the selected
clock could have a detrimental impact on the accuracy of
the output clock.
Anomalies, whether affecting signal purity or signal
frequency, could induce jitter or frequency offsets in the
output clock, leading to anomalous behavior. Anomalies
on the selected clock, therefore, have to be detected as
they occur and the phase locked loop must be temporarily
isolated until the clock is once again pure. The clock
monitoring process cannot be used for this because the
high degree of accuracy required dictates that the
process be slow.
To achieve the immediacy required by the phase locked
loop requires an alternative mechanism. The phase
locked loop itself contains appropriate circuitry, based
around the phase detector, and isolates itself from the
selected reference source as soon as a signal impurity is
detected. It can likewise respond to frequency offsets
outside the permitted range since these result in
saturation of the phase detector. When the phase locked
loop is isolated from the reference source, it is essentially
operating in a Holdover state; this is preferable to feeding
the loop with a standby source, either temporarily or
permanently, since excessive phase excursions on the
output clock are avoided. Anomalies detected by the
phase detector are integrated in a leaky bucket
accumulator. Occasional anomalies do not cause the
accumulator to cross the alarm setting threshold, so the
selected reference source is retained. Persistent
anomalies cause the alarm setting threshold to be
crossed and result in the selected reference source being
rejected.
ACS8509 SETS
DATASHEET
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