ACS8509 Semtech Corporation, ACS8509 Datasheet - Page 42

• Manufacturer Part Number: ACS8509
• Description: Synchronous Equipment Timing Source for Sonet or SDH Network Elements
• Manufacturer: Semtech Corporation

If a Master device fails, the Slave has to take over
responsibility for the generation of the output clocks,
including the 8 kHz and 2 kHz Frame and Multi-Frame
clocks. The Slave device is also given responsibility for
building the priority table and performing the reference
switching operations. The Slave device, therefore, adopts
a more active role when the Master has failed. The
cnfg_mode register 34 (Hex) Bit 1 contains the
Master/Slave control bit to determine the designation of
the device.
To restore redundancy protection, the Master has to be
repaired and replaced. When this occurs, the new Master
cannot immediately adopt its normal role because it must
not cause phase hits on the output clocks. It has,
therefore, to adopt a subordinate role to the active Slave
device, at least until such time as it has acquired
alignment to the 8 kHz and 2 kHz frame and Multi-Frame
clocks and the priority table of the Slave device; then,
when a switch-back (restoration) is ordered, the Master
can take over responsibility. These activities, in Master or
Slave operation, are summarized in Table 15 and
described in detail in Application Note AN-SETS-2.
Alignment of Priority Tables in Master and Slave
ACS8509
Correct protection will only be achieved by connecting
individual reference sources to the same input ports on
each device and priority tables in each device must be
aligned to each other.
The Master device must take account of the availability of
each reference source seen by another device and a
Slave device must adopt the same order of priority as the
Master device (except that the Slave's highest-priority
input is SEC3). Both devices monitor the reference
sources and decide the availability of each source; if the
failure of a reference source is seen by both devices, they
will both update their priority tables - however, if the
reference source failure is only seen by one device and
not by both, the priority tables could get out of step: this
could be catastrophic if it resulted in two devices choosing
different reference sources since any slight differences in
frequency variation over time (e.g. wander) would mis-
align the phase of the 8 kHz Frame and 2 kHz Multi-Frame
clocks produced by the individual devices, resulting in
phase hits on switchover. It is therefore important that the
same priority table be built by each device, using the
reference source availability seen by each device.
Revision 2.00/January 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
FINAL
Page 42
The monitoring of the reference sources performed by a
Master ACS8509 results in a list of available sources
being placed in a sts_valid_sources register. This
information is used within the device as one of the masks
used to build the device's priority table. The information is
passed to the Slave device and used to configure the
cnfg_sts_remote_sources_valid register so that it can use
it as a mask in building its own priority tables. The
information is passed between devices using the
microprocessor port.
Alignment of the Selection of Reference Sources
for T
ACS8509
As stated previously, there is no need to align the phases
of the T
a need, however, to ensure that all devices select the
same reference source. But, since there is no Holdover
mode required for the generation of the T
every reference source is continuously monitored within
each device, it is permissible to rely on external
intelligence to command a switchover to an alternative
source should the selected one fail. The time delay
involved in detecting the failure, indicating it to the
outside and selecting a new source, will result only in the
SSU/BITS entering its Holdover mode for a short time.
Alignment of the Phases of the 8 kHz and 2 kHz
Clocks in both Master and Slave ACS8509
In addition to aligning the edges of the T
Master and Slave devices, it is necessary to align the
edges of the Frame and Multi-Frame clocks. If this is not
performed, frame alignment may be lost in distant
equipment on switch-over to an alternative device,
resulting in anomalous network operation of a very
serious nature.
In accordance with the alignment mechanism used with
the main T
paragraphs of this section), whereby the 6.48 MHz output
of the Master device is supplied to the Slave device, the
alignment of both the 8 kHz and 2 kHz clocks is
accomplished (they are already synchronous to the T
clocks) by feeding the 2 kHz clock of the Master device
into the Slave device. The Multi-Frame Sync clock output
of the Slave device is also fed to the Sync2K input of the
Master device. Alignment of the Multi-Frame Sync input
occurs only when cnfg_mode register, bit 3, address
34Hex External 2 kHz Sync Enable is set to 1.
OUT4
OUT4
Generation in the Master and Slave
OUT0
outputs in Master and Slave devices. There is
clock (described in the opening
ACS8509 SETS
OUT0
DATASHEET
OUT4
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outputs of
clock, and
OUT0