ACS8509 Semtech Corporation, ACS8509 Datasheet - Page 40

• Manufacturer Part Number: ACS8509
• Description: Synchronous Equipment Timing Source for Sonet or SDH Network Elements
• Manufacturer: Semtech Corporation

the input and output cycles will be constantly moving past
each other; however, this variation will itself be cyclical
over time unless the input and output are not locked.
Lost_Phase mode
Lost-phase mode is entered when the current phase
error, as measured within the DPLL, is larger than a preset
limit (see register 04, bits 5:3), as a result of a frequency
or phase transient on the selected reference source.
This mode is similar in behavior to the Pre-locked or
Pre-locked(2) modes, although in this mode the DPLL is
attempting to regain lock to the same reference rather
than attempt lock to a new reference.
If the DPLL cannot regain lock within 100 s, the source is
disqualified, and one of the following transitions takes
place:
1. Go to Pre-Locked(2);
- If a known-good standby source is available.
2. Go to Holdover;
- If no standby sources are available.
Holdover mode
The Holdover mode is used when the ACS8509 has been
in Locked mode for long enough to acquire stable
frequency data, but the final selected reference source
has become unavailable and a replacement has not yet
been qualified for selection. In Holdover mode, the
ACS8509 provides the timing and synchronization signals
to maintain the Network Element (NE), but they are not
phase locked to any input reference source.
The timing is based on a stored value of the frequency
ratio obtained during the last Locked mode period.
To allow for further development of the way the internal
algorithm operates, and to allow for customized switching
behavior, the switch to and from Holdover state may be
controlled by external software.
The device must be set in either “manual” mode or
“automatic” mode:
1. Register cnfg_mode bit holdover offset enable set high
(manual mode). The Holdover frequency is determined by
the value in register cnfg_holdover_offset. This is a 19 bit
signed number, with a LSB resolution of 0.0003 ppm,
which gives an adjustment range of ±80 ppm. This value
can be derived from a reading of the register
sts_curr_inc_offset (addr 0D, 0C and 07) which gives, in
Revision 2.00/January 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
FINAL
Page 40
the same format, an indication of the current output
frequency deviation, which would be read when the
device is locked. If required, this value could be read by an
external microcontroller and averaged over the time
required. The averaged value could then be fed to the
cnfg_holdover_offset register ready for setting of the
averaged frequency value when the device enters
Holdover mode. The sts_curr_inc_offset value is internally
derived from the Digital Phase Locked Loop (DPLL)
integral path value, which already represents a well
averaged measure of the current frequency, depending
on the loop bandwidth selected.
2. Register cnfg_mode bit holdover offset enable set low
(automatic mode). In automatic control, the device can be
run in one of two ways:
2.1 Register cnfg_holdover_offset register 40 bit 7 auto
holdover averaging is set high. The value is averaged
internally over 32 samples at 32 seconds apart, giving the
average frequency over approximately the last 20
minutes. The proportional DPLL path is ignored so that
recent signal disturbances do not affect the Holdover
frequency value. If the device has been previously
correctly locked, missing pulses in the input clock stream
fed to the SETS IC are ignored, hence also avoiding any
frequency disturbances to the output frequency value
when an input clock source fails.
2.2 Register cnfg_holdover_offset register 40 bit 7 auto
holdover averaging is set low. This simply freezes the
DPLL at the current frequency (as reported by the
sts_curr_inc_offset register). The proportional DPLL path
is ignored so that recent signal disturbances do not affect
the Holdover frequency value.
Automatic control with internal averaging (option 2.1) is
the default condition. If the TCXO frequency is varying due
to temperature fluctuations in the room, then the
instantaneous value can be different from the average
value, and then it may be possible to exceed the
0.05 ppm limit (depending on how extreme the
temperature fluctuations are). It is advantageous to
shield the TCXO to slow down frequency changes due to
drift and external temperature fluctuations.
The frequency accuracy of Holdover mode has to meet the
ITU-T, ETSI and Telcordia performance requirements. The
performance of the external oscillator clock is critical in
this mode, although only the frequency stability is
important - the stability of the output clock in Holdover is
directly related to the stability of the external oscillator.
ACS8509 SETS
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