ADC12030CIWM National Semiconductor, ADC12030CIWM Datasheet - Page 29

• Manufacturer Part Number: ADC12030CIWM
• Description: Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
• Manufacturer: National Semiconductor

Application Hints
1.3 CS Low Continuously Considerations
When CS is continuously low, it is important to transmit the
exact number of SCLK pulses that the ADC expects. Not do-
ing so will desynchronize the serial communications to the
ADC. When the supply power is first applied to the ADC, it
will expect to see 13 SCLK pulses for each I/O transmission.
The number of SCLK pulses that the ADC expects to see is
the same as the digital output word length. The digital output
word length is controlled by the Data Out (DO) format. The
DO format maybe changed any time a conversion is started
or when the sign bit is turned on or off. The table below de-
tails out the number of clock periods required for different
DO formats:
If erroneous SCLK pulses desynchronize the communica-
tions, the simplest way to recover is by cycling the power
supply to the device. Not being able to easily resynchronize
the device is a shortcoming of leaving CS low continuously.
The number of clock pulses required for an I/O exchange
may be different for the case when CS is left low continu-
ously vs the case when CS is cycled. Take the I/O sequence
detailed in Figure 7 (Typical Power Supply Sequence) as an
example. The table below lists the number of SCLK pulses
required for each instruction:
12-Bit MSB or LSB First
16-Bit MSB or LSB first
Auto Cal
Read Status
Read Status
12-Bit + Sign Conv 1
12-Bit + Sign Conv 2
8-Bit MSB or LSB First
Instruction
DO Format
Continuously
13 SCLKs
13 SCLKs
13 SCLKs
13 SCLKs
13 SCLKs
(Continued)
CS Low
SIGN OFF
SIGN ON
SIGN OFF
SIGN ON
SIGN OFF
SIGN ON
FIGURE 8. Changing the ADC’s Conversion Configuration
CS Strobed
Number of
13 SCLKs
Expected
8 SCLKs
8 SCLKs
8 SCLKs
8 SCLKs
SCLKs
12
13
16
17
8
9
29
1.4 Analog Input Channel Selection
The data input on DI also selects the channel configuration
for a particular A/D conversion (see Tables 2, 3, 4 and Table
5 ). In Figure 8 the only times when the channel configuration
could be modified would be during I/O sequences 1, 4, 5 and
6. Input channels are reselected before the start of each new
conversion. Shown below is the data bit stream required on
DI, during I/O sequence number 4 in Figure 8 , to set CH1 as
the positive input and CH0 as the negative input for the dif-
ferent versions of ADCs:
Where X can be a logic high (H) or low (L).
1.5 Power Up/Down
The ADC may be powered down at any time by taking the
PD pin HIGH or by the instruction input on DI (see Tables 5,
6 , and the Power Up/Down timing diagrams). When the ADC
is powered down in this way, the circuitry necessary for an
A/D conversion is deactivated. The circuitry necessary for
digital I/O is kept active. Hardware power up/down is con-
trolled by the state of the PD pin. Software power-up/down is
controlled by the instruction issued to the ADC. If a software
power up instruction is issued to the ADC while a hardware
power down is in effect (PD pin high) the device will remain
in the power-down state. If a software power down instruc-
tion is issued to the ADC while a hardware power up is in ef-
fect (PD pin low), the device will power down. When the de-
vice is powered down by software, it may be powered up by
either issuing a software power up instruction or by taking
PD pin high and then low. If the power down command is is-
sued during an A/D conversion, that conversion is disrupted.
Therefore, the data output after power up cannot be relied
upon.
ADC12H030
ADC12H032
ADC12H034
ADC12H038
ADC12030
ADC12032
ADC12034
ADC12038
Number
Part
DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7
L
L
L
L
H
H
H
H
L
L
L
L
DI Data
L
L
L
L
H
H
L
L
DS011354-37
H
L
L
L
www.national.com
X
X
H
L
X
X
X
L