ADC12030CIWM National Semiconductor, ADC12030CIWM Datasheet - Page 35

• Manufacturer Part Number: ADC12030CIWM
• Description: Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
• Manufacturer: National Semiconductor

Application Hints
MUXOUT2 tied to A/DIN2 the internal multiplexer switch on
resistance is typically 1.6 k . The A/DIN1 and A/DIN2 mux
on resistance is typically 750 .
6.0 INPUT SOURCE RESISTANCE
For low impedance voltage sources (
charging current will decay, before the end of the S/H’s ac-
quisition time of 2 µs (10 CCLK periods with f
a value that will not introduce any conversion errors. For high
source impedances, the S/H’s acquisition time can be in-
creased to 18 or 34 CCLK periods. For less ADC resolution
and/or slower CCLK frequencies the S/H’s acquisition time
may be decreased to 6 CCLK periods. To determine the
number of clock periods (N
with a specific source impedance for the various resolutions
the following equations can be used:
Where f
and R
ample, operating with a resolution of 12 Bits+sign, a 5 MHz
clock frequency and maximum acquistion time of 34 conver-
sion clock periods the ADC’s analog inputs can handle a
source impedance as high as 6 k . The acquisition time may
also be extended to compensate for the settling or response
time of external circuitry connected between the MUXOUT
and A/DIN pins.
The acquisition time t
and ended by a rising edge of CCLK (see timing diagrams).
If SCLK and CCLK are asynchronous one extra CCLK clock
period may be inserted into the programmed acquisition time
for synchronization. Therefore with asnychronous SCLK and
CCLKs the acquisition time will change from conversion to
conversion.
7.0 INPUT BYPASS CAPACITANCE
External capacitors (0.01 µF–0.1 µF) can be connected be-
tween the analog input pins, CH0–CH7, and analog ground
to filter any noise caused by inductive pickup associated with
long input leads. These capacitors will not degrade the con-
version accuracy.
12 Bit + Sign N
8 Bit + Sign N
S
C
is the external source resistance in k . As an ex-
is the conversion clock (CCLK) frequency in MHz
C
C
= [ R
= [ R
A
is started by a falling edge of SCLK
S
S
c
) required for the acquisition time
+ 2.3] x f
+ 2.3] x f
(Continued)
C
C
x 0.824
x 0.57
<
600 ), the input
C
= 5 MHz), to
35
8.0 NOISE
The leads to each of the analog multiplexer input pins should
be kept as short as possible. This will minimize input noise
and clock frequency coupling that can cause conversion er-
rors. Input filtering can be used to reduce the effects of the
noise sources.
9.0 POWER SUPPLIES
Noise spikes on the V
conversion errors; the comparator will respond to the noise.
The ADC is especially sensitive to any power supply spikes
that occur during the auto-zero or linearity correction. The
minimum power supply bypassing capacitors recommended
are low inductance tantalum capacitors of 10 µF or greater
paralleled with 0.1 µF monolithic ceramic capacitors. More or
different bypassing may be necessary depending on the
overall system requirements. Separate bypass capacitors
should be used for the V
close as possible to these pins.
10.0 GROUNDING
The ADC12030/2/4/8’s performance can be maximized
through proper grounding techniques. These include the use
of separate analog and digital ground planes. The digital
ground plane is placed under all components that handle
digital signals, while the analog ground plane is placed under
all components that handle analog signals. The digital and
analog ground planes are connected together at only one
point, either the power supply ground or at the pins of the
ADC. This greatly reduces the occurence of ground loops
and noise.
Shown in Figure 18 is the ideal ground plane layout for the
ADC12038 along with ideal placement of the bypass capaci-
tors. The circuit board layout shown in Figure 18 uses three
bypass capacitors: 0.01 µF (C1) and 0.1 µF (C2) surface
mount capacitors and 10 µF (C3) tantalum capacitor.
A
+
A
+
and V
and V
D
D
+
+
supply lines can cause
supplies and placed as
www.national.com