PIC12CE67 Microchip Technology, PIC12CE67 Datasheet - Page 10

• Manufacturer Part Number: PIC12CE67
• Description: 8-Pin/ 8-Bit CMOS Microcontroller with A/D Converter and EEPROM Data Memory
• Manufacturer: Microchip Technology

FIGURE 3-2:
EXAMPLE 3-1:
PIC12CE67X
3.1
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
is shown in Figure 3-2.
DS40181B-page 10
1. MOVLW 55h
2. MOVWF GPIO
3. CALL
4. BSF
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruc-
tion is “flushed” from the pipeline while the new instruction is being fetched and then executed.
OSC2/CLKOUT
INTRC modes)
Clocking Scheme/Instruction Cycle
(EXTRC and
SUB_1
GPIO, BIT3 (Forced NOP)
OSC1
CLOCK/INSTRUCTION CYCLE
Q4
PC
Q2
Q3
Q1
INSTRUCTION PIPELINE FLOW
Q1
Execute INST (PC-1)
Fetch 1
Fetch INST (PC)
Tcy0
Q2
PC
Q3
Execute 1
Fetch 2
Tcy1
Q4
Preliminary
Q1
Execute 2
Fetch 3
Tcy2
Execute INST (PC)
Fetch INST (PC+1)
Q2
PC+1
3.2
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute
are pipelined such that fetch takes one instruction
cycle while decode and execute takes another
instruction cycle. However, due to the pipelining, each
instruction effectively executes in one cycle. If an
instruction causes the program counter to change
(e.g. GOTO ) then two cycles are required to complete
the instruction (Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is
latched into the “Instruction Register" (IR) in cycle
Q1. This instruction is then decoded and executed
during the Q2, Q3, and Q4 cycles. Data memory is
read during Q2 (operand read) and written during Q4
(destination write).
Q3
Execute 3
Fetch 4
Tcy3
Instruction Flow/Pipelining
Q4
Q1
Fetch SUB_1
Execute INST (PC+1)
Flush
Tcy4
Fetch INST (PC+2)
Q2
1998 Microchip Technology Inc.
PC+2
Q3
Execute SUB_1
Q4
Tcy5
Internal
phase
clock