PIC12CE67 Microchip Technology, PIC12CE67 Datasheet - Page 26

• Manufacturer Part Number: PIC12CE67
• Description: 8-Pin/ 8-Bit CMOS Microcontroller with A/D Converter and EEPROM Data Memory
• Manufacturer: Microchip Technology

FIGURE 5-2:
PIC12CE67X
TABLE 5-1:
5.4
5.4.1
Any instruction which writes, operates internally as a
read followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result back
to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSF operation on bit5
of GPIO will cause all eight bits of GPIO to be read into
the CPU. Then the BSF operation takes place on bit5
and GPIO is written to the output latches. If another bit
of GPIO is used as a bi-directional I/O pin (e.g., bit0)
and it is defined as an input at this time, the input signal
present on the pin itself would be read into the CPU
and rewritten to the data latch of this particular pin,
overwriting the previous content. As long as the pin
stays in the input mode, no problem occurs. However,
if bit0 is switched to an output, the content of the data
latch may now be unknown.
Reading the port register, reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read-modify-write instructions
(ex. BCF, BSF, etc.) on a port, the value of the port pins
is read, the desired operation is done to this value, and
this value is then written to the port latch.
DS40181B-page 26
Address
Instruction
Instruction
85h
81h
03h
05h
Legend: Shaded cells not used by Port Registers, read as ‘0’, — = unimplemented, read as '0', x = unknown, u = unchanged,
Note 1: The IRP and RP1 bits are reserved on the PIC12CE67X, always maintain these bits clear.
executed
GP5:GP0
fetched
I/O Programming Considerations
BI-DIRECTIONAL I/O PORTS
q = see tables in Section 9.4 for possible values.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
MOVWF GPIO
TRIS
OPTION
STATUS
GPIO
Name
PC
SUCCESSIVE I/O OPERATION
SUMMARY OF PORT REGISTERS
GPPU
IRP
Bit 7
SCL
—
MOVF GPIO,W
MOVWF GPIO
(1)
(Write to
GPIO)
Port pin
written here
PC + 1
INTEDG
RP1
Bit 6
SDA
—
(1)
MOVF GPIO,W
GPIO Data Direction Register
T0CS
Bit 5
(Read
GP5
RP0
Port pin
sampled here
GPIO)
NOP
PC + 2
Preliminary
T0SE
Bit 4
GP4
TO
Bit 3
PSA
GP3
PD
PC + 3
NOP
NOP
Example 5-1 shows the effect of two sequential read-
modify-write instructions on an I/O port.
EXAMPLE 5-1:
;Initial GPIO Settings
; GPIO<5:3> Inputs
; GPIO<2:0> Outputs
;
;
;
;
;Note that the user may have expected the pin
;values to be --00 pppp. The 2nd BCF caused
;GP5 to be latched as the pin value (High).
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage the
chip.
BCF
BCF
MOVLW 007h
TRIS
Bit 2
GP2
PS2
Z
GPIO, 5
GPIO, 4
GPIO
This example shows a write to GPIO followed
by a read from GPIO.
Data setup time = (0.25 T
where: T
Therefore, at higher clock frequencies, a
write followed by a read may be problematic.
Bit 1
GP1
PS1
DC
Bit 0
T
PS0
GP0
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
CY
PD
C
;--01 -ppp
;--10 -ppp
;--10 -ppp
;
= instruction cycle.
= propagation delay
GPIO latch
----------
1998 Microchip Technology Inc.
--11 1111
1111 1111
0001 1xxx
11xx xxxx
Power-on
Value on
Reset
CY
--11 pppp
--11 pppp
--11 pppp
– T
GPIO pins
----------
PD
--11 1111
1111 1111
000q quuu
11uu uuuu
)
Value on
all other
Resets