PIC17C42 Microchip Technology, PIC17C42 Datasheet - Page 211

• Manufacturer Part Number: PIC17C42
• Description: High-Performance 8-Bit CMOS EPROM/ROM Microcontroller
• Manufacturer: Microchip Technology

APPENDIX A: MODIFICATIONS
The following is the list of modifications over the
PIC16CXX microcontroller family:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Multiple Interrupt vectors added. This can
11. Stack size is increased to 16 deep.
12. BSR register for data memory paging.
13. Wake up from SLEEP operates slightly differ-
14. The Oscillator Start-Up Timer (OST) and
15. PORTB interrupt on change feature works on all
16. TMR0 is 16-bit plus 8-bit prescaler.
17. Second indirect addressing register added
18. Hardware multiplier added (8 x 8
19. Peripheral modules operate slightly differently.
20. Oscillator modes slightly redefined.
21. Control/Status bits and registers have been
22. Addition of a test mode pin.
23. In-circuit serial programming is not imple-
1996 Microchip Technology Inc.
Instruction word length is increased to 16-bit.
This allows larger page sizes both in program
memory (8 Kwords verses 2 Kwords) and regis-
ter file (256 bytes versus 128 bytes).
Four modes of operation: microcontroller, pro-
tected microcontroller, extended microcontroller,
and microprocessor.
22 new instructions.
The MOVF , TRIS and OPTION instructions have
been removed.
4 new instructions for transferring data between
data memory and program memory. This can be
used to “self program” the EPROM program
memory.
Single cycle data memory to data memory trans-
fers possible ( MOVPF and MOVFP instructions).
These instructions do not affect the Working reg-
ister (WREG).
W register (WREG) is now directly addressable.
A PC high latch register (PCLATH) is extended
to 8-bits. The PCLATCH register is now both
readable and writable.
Data memory paging is redefined slightly.
DDR registers replaces function of TRIS regis-
ters.
decrease the latency for servicing the interrupt.
ently.
Power-Up Timer (PWRT) operate in parallel and
not in series.
eight port pins.
(FSR1 and FSR2). Configuration bits can select
the FSR registers to auto-increment, auto-dec-
rement, remain unchanged after an indirect
address.
(PIC17C43 and PIC17C44 only).
placed in different registers and the control bit
for globally enabling interrupts has inverse
polarity.
mented.
This document was created with FrameMaker 4 0 4
16-bit)
APPENDIX B: COMPATIBILITY
To convert code written for PIC16CXX to PIC17CXX,
the user should take the following steps:
1.
2.
3.
4.
5.
6.
7.
8.
9.
To convert code from the PIC17C42 to all the other
PIC17C4X devices, the user should take the following
steps.
1.
2.
3.
Note:
Remove any TRIS and OPTION instructions,
and implement the equivalent code.
Separate the interrupt service routine into its
four vectors.
Replace:
MOVF
with:
MOVFP
Replace:
MOVF
MOVWF
with:
MOVPF
or
MOVFP
Ensure that all bit names and register names are
updated to new data memory map location.
Verify data memory banking.
Verify mode of operation for indirect addressing.
Verify peripheral routines for compatibility.
Weak pull-ups are enabled on reset.
If the hardware multiply is to be used, ensure
that any variables at address 18h and 19h are
moved to another address.
Ensure that the upper nibble of the BSR was not
written with a non-zero value. This may cause
unexpected operation since the RAM bank is no
longer 0.
The disabling of global interrupts has been
enhanced so there is no additional testing of the
GLINTD bit after a BSF
instruction.
If REG1 and REG2 are both at addresses
greater then 20h, two instructions are
required.
MOVFP
MOVPF
REG1, REG2 ; Addr(REG2)<20h
REG1, W
REG1, WREG
REG1, W
REG2
REG1, REG2 ; Addr(REG1)<20h
REG1, WREG ;
WREG, REG2 ;
PIC17C4X
CPUSTA,
DS30412C-page 211
GLINTD