PIC17C42 Microchip Technology, PIC17C42 Datasheet - Page 77

• Manufacturer Part Number: PIC17C42
• Description: High-Performance 8-Bit CMOS EPROM/ROM Microcontroller
• Manufacturer: Microchip Technology

12.1.3.3.1 MAX RESOLUTION/FREQUENCY FOR
The use of an external clock for the PWM time-base
(Timer1 or Timer2) limits the PWM output to a maxi-
mum resolution of 8-bits. The PWxDCL<7:6> bits must
be kept cleared. Use of any other value will distort the
PWM output. All resolutions are supported when inter-
nal clock mode is selected. The maximum attainable
frequency is also lower. This is a result of the timing
requirements of an external clock input for a timer (see
the Electrical Specification section). The maximum
PWM frequency, when the timers clock source is the
RB4/TCLK12 pin, is shown in Table 12-3 (standard res-
olution mode).
12.2
Timer3 is a 16-bit timer consisting of the TMR3H and
TMR3L registers. TMR3H is the high byte of the timer
and TMR3L is the low byte. This timer has an associ-
ated 16-bit period register (PR3H/CA1H:PR3L/CA1L).
This period register can be software configured to be a
second 16-bit capture register.
When the TMR3CS bit (TCON1<2>) is clear, the timer
increments every instruction cycle (Fosc/4). When
TMR3CS is set, the timer increments on every falling
edge of the RB5/TCLK3 pin. In either mode, the
TMR3ON bit must be set for the timer to increment.
When TMR3ON is clear, the timer will not increment or
set the TMR3IF bit.
TABLE 12-4:
Address
16h, Bank 3
17h, Bank 3
10h, Bank 2
11h, Bank 2
16h, Bank 1
17h, Bank 1
07h, Unbanked INTSTA
06h, Unbanked CPUSTA
10h, Bank 3
11h, Bank 3
12h, Bank 3
13h, Bank 3
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends on conditions,
1996 Microchip Technology Inc.
Timer3
shaded cells are not used by PWM.
EXTERNAL CLOCK INPUT
Name
TCON1
TCON2
TMR1
TMR2
PIR
PIE
PW1DCL
PW2DCL
PW1DCH
PW2DCH
REGISTERS/BITS ASSOCIATED WITH PWM
Timer1 register
Timer2 register
CA2OVF
CA2ED1
RBIE
Bit 7
RBIF
PEIF
DC1
DC1
DC9
DC9
—
CA2ED0
CA1OVF
TMR3IF
TMR3IE
T0CKIF
Bit 6
DC0
DC0
DC8
DC8
—
PWM2ON
TM2PW2
CA1ED1
TMR2IF
TMR2IE
STKAV
Bit 5
T0IF
DC7
DC7
—
PWM1ON
CA1ED0
TMR1IE
GLINTD
TMR1IF
INTF
Bit 4
DC6
DC6
—
—
Timer3 has two modes of operation, depending on the
CA1/PR3 bit (TCON2<3>). These modes are:
• One capture and one period register mode
• Dual capture register mode
The PIC17C4X has up to two 16-bit capture registers
that capture the 16-bit value of TMR3 when events are
detected on capture pins. There are two capture pins
(RB0/CAP1 and RB1/CAP2), one for each capture reg-
ister. The capture pins are multiplexed with PORTB
pins. An event can be:
• a rising edge
• a falling edge
• every 4th rising edge
• every 16th rising edge
Each 16-bit capture register has an interrupt flag asso-
ciated with it. The flag is set when a capture is made.
The capture module is truly part of the Timer3 block.
Figure 12-7 and Figure 12-8 show the block diagrams
for the two modes of operation.
CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000
CA2IF
CA2IE
Bit 3
PEIE
DC5
DC5
T16
TO
—
—
TMR3CS TMR2CS
T0CKIE
CA1IF
CA1IE
Bit 2
DC4
DC4
PD
—
—
TXIF
TXIE
Bit 1
T0IE
DC3
DC3
—
—
—
TMR1CS
PIC17C4X
RCIF
RCIE
INTE
Bit 0
DC2
DC2
—
—
—
DS30412C-page 77
0000 0000
xxxx xxxx
xxxx xxxx
0000 0010
0000 0000
0000 0000
--11 11--
xx-- ----
xx0- ----
xxxx xxxx
xxxx xxxx
Power-on
Value on
Reset
Value on all
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 0010
0000 0000
0000 0000
--11 qq--
uu-- ----
uu0- ----
uuuu uuuu
uuuu uuuu
(Note1)
resets
other