PIC17C42 Microchip Technology, PIC17C42 Datasheet - Page 79

• Manufacturer Part Number: PIC17C42
• Description: High-Performance 8-Bit CMOS EPROM/ROM Microcontroller
• Manufacturer: Microchip Technology

12.2.2
This mode is selected by setting CA1/PR3. A block dia-
gram is shown in Figure 12-8. In this mode, TMR3 runs
without a period register and increments from 0000h to
FFFFh and rolls over to 0000h. The TMR3 interrupt
Flag (TMR3IF) is set on this roll over. The TMR3IF bit
must be cleared in software.
Registers PR3H/CA1H and PR3L/CA1L make a 16-bit
capture register (Capture1). It captures events on pin
RB0/CAP1. Capture mode is configured by the
CA1ED1 and CA1ED0 bits. Capture1 Interrupt Flag bit
(CA1IF) is set on the capture event. The corresponding
interrupt mask bit is CA1IE. The Capture1 Overflow
Status bit is CA1OVF.
FIGURE 12-8: TIMER3 WITH TWO CAPTURE REGISTERS BLOCK DIAGRAM
TABLE 12-5:
16h, Bank 3
17h, Bank 3
12h, Bank 2
13h, Bank 2
16h, Bank 1
17h, Bank 1
07h, Unbanked INTSTA
06h, Unbanked CPUSTA
16h, Bank 2
17h, Bank 2
14h, Bank 3
15h, Bank 3
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition,
Note 1: Other (non power-up) resets include: external reset through MCLR and WDT Timer Reset.
Address
1996 Microchip Technology Inc.
RB0/CAP1
RB5/TCLK3
RB1/CAP2
DUAL CAPTURE REGISTER MODE
shaded cells are not used by Capture.
CA1ED1, CA1ED0
(TCON1<5:4>)
Fosc/4
Name
TCON1
TCON2
TMR3L
TMR3H
PIR
PIE
PR3L/CA1L
PR3H/CA1H Timer3 period register, high byte/capture1 register, high byte
CA2L
CA2H
REGISTERS ASSOCIATED WITH CAPTURE
TMR3CS
(TCON1<2>)
Edge Select
Prescaler Select
Edge Select
Prescaler Select
TMR3 register; low byte
TMR3 register; high byte
Timer3 period register, low byte/capture1 register, low byte
Capture2 low byte
Capture2 high byte
CA2ED1 CA2ED0
CA2OVF CA1OVF PWM2ON
2
RBIF
RBIE
Bit 7
PEIF
—
0
1
CA2ED1, CA2ED0
(TCON1<7:6>)
2
(TCON2<2>)
TMR3ON
TMR3IF
TMR3IE
T0CKIF
Bit 6
—
CA1ED1
TMR2IE
TMR2IF
STKAV
Bit 5
T0IF
PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000
CA1ED0
TMR1IF
TMR1IE
GLINTD
Bit 4
INTF
Capture Enable
Capture Enable
CA2IF
CA2IE
PEIE
The Capture2 overflow status flag bit is double buff-
ered. The master bit is set if one captured word is
already residing in the Capture2 register and another
“event” has occurred on the RB1/CA2 pin. The new
event will not transfer the TMR3 value to the capture
register which protects the previous unread capture
value. When the user reads both the high and the low
bytes (in any order) of the Capture2 register, the master
overflow bit is transferred to the slave overflow bit
(CA2OVF) and then the master bit is reset. The user
can then read TCON2 to determine the value of
CA2OVF.
The operation of the Capture1 feature is identical to
Capture2 (as described in Section 12.2.1).
Bit 3
T16
PR3H/CA1H
TO
TMR3H
CA2H
TMR3CS TMR2CS TMR1CS 0000 0000
T0CKIE
CA1IF
CA1IE
Bit 2
PD
PR3L/CA1L
Bit 1
TXIF
TXIE
T0IE
—
TMR3L
CA2L
RCIF
RCIE
INTE
Bit 0
—
PIC17C4X
xxxx xxxx
xxxx xxxx
0000 0010
0000 0000
0000 0000
--11 11--
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
Power-on
Value on
Reset
DS30412C-page 79
Set CA1IF
(PIR<2>)
Set CA2IF
(PIR<3>)
Set TMR3IF
(PIR<6>)
other resets
Value on all
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 0010
0000 0000
0000 0000
--11 qq--
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
(Note1)