XC3S250E Xilinx, Inc., XC3S250E Datasheet - Page 2

• Manufacturer Part Number: XC3S250E
• Description: Spartan-3E FPGA Family
• Manufacturer: Xilinx, Inc.

DS312-1 (v1.1) March 21, 2005
Introduction
The Spartan™-3E family of Field-Programmable Gate
Arrays (FPGAs) is specifically designed to meet the needs
of high volume, cost-sensitive consumer electronic applica-
tions. The five-member family offers densities ranging from
100,000 to 1.6 million system gates, as shown in
The Spartan-3E family builds on the success of the earlier
Spartan-3 family by increasing the amount of logic per I/O,
significantly reducing the cost per logic cell. New features
improve system performance and reduce the cost of config-
uration. These Spartan-3E enhancements, combined with
advanced 90 nm process technology, deliver more function-
ality and bandwidth per dollar than was previously possible,
setting new standards in the programmable logic industry.
Because of their exceptionally low cost, Spartan-3E FPGAs
are ideally suited to a wide range of consumer electronics
applications, including broadband access, home network-
ing, display/projection, and digital television equipment.
The Spartan-3E family is a superior alternative to mask pro-
grammed ASICs. FPGAs avoid the high initial cost, the
lengthy development cycles, and the inherent inflexibility of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.
Features
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•
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Table 1: Summary of Spartan-3E FPGA Attributes
Notes:
1.
DS312-1 (v1.1) March 21, 2005
Advance Product Specification
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
Device
Very low cost, high-performance logic solution for
high-volume, consumer-oriented applications
Proven advanced 90-nanometer process technology
Multi-voltage, multi-standard SelectIO™ interface pins
-
-
By convention, one Kb is equivalent to 1,024 bits.
Up to 376 I/O pins or 156 differential signal pairs
LVCMOS, LVTTL, HSTL, and SSTL single-ended
signal standards
System
Gates
1200K
1600K
100K
250K
500K
© 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.
Equivalent
10,476
19,512
33,192
Logic
2,160
5,508
Cells
R
Rows Columns
22
34
46
60
76
(One CLB = Four Slices)
All other trademarks are the property of their respective owners.
16
26
34
46
58
CLB Array
CLBs
1,164
2,168
3,688
Total
240
612
Table
06
0
www.xilinx.com
1.
14,752
Slices
2,448
4,656
8,672
Total
960
0
Spartan-3E FPGA Family:
Introduction and Ordering
Information
Advance Product Specification
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•
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RAM bits
Distributed
136K
231K
15K
38K
73K
-
-
-
Abundant, flexible logic resources
-
-
-
-
-
Hierarchical SelectRAM™ memory architecture
-
-
Up to eight Digital Clock Managers (DCMs)
-
-
-
-
Eight global clocks and eight clocks for each half of
device, plus abundant low-skew routing
Configuration interface to industry-standard PROMs
-
-
-
Complete Xilinx ISE™, WebPACK™ development
system support
MicroBlaze™, PicoBlaze™ embedded processor cores
Fully compliant 32-/64-bit 33/66 MHz PCI support
Low-cost QFP and BGA packaging options
-
-
(1)
True LVDS, RSDS, mini-LVDS differential I/O
3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
Enhanced Double Data Rate (DDR) support
Densities up to 33,192 logic cells, including
optional shift register or distributed RAM support
Efficient wide multiplexers, wide logic
Fast look-ahead carry logic
Enhanced 18 x 18 multipliers with optional pipeline
IEEE 1149.1/1532 JTAG programming/debug port
Up to 648 Kbits of fast block RAM
Up to 231 Kbits of efficient distributed RAM
Clock skew elimination (delay locked loop)
Frequency synthesis, multiplication, division
High-resolution phase shifting
Wide frequency range (5 MHz to over 300 MHz)
Low-cost, space-saving SPI serial Flash PROM
x8 or x8/x16 parallel NOR Flash PROM
Low-cost Xilinx Platform Flash with JTAG
Common footprints support easy density migration
Pb-free packaging options
bits
Block
216K
360K
504K
648K
RAM
72K
(1)
Multipliers DCMs
Dedicated
12
20
28
36
4
2
4
4
8
8
Maximum
User I/O
108
172
232
304
376
Differential
Maximum
I/O Pairs
124
156
40
68
92
1