XC3S250E Xilinx, Inc., XC3S250E Datasheet - Page 55

• Manufacturer Part Number: XC3S250E
• Description: Spartan-3E FPGA Family
• Manufacturer: Xilinx, Inc.

Functional Description
Stabilizing DCM Clocks Before User Mode
The STARTUP_WAIT attribute shown in
delays the end of the FPGA’s configuration process until
after the DCM locks to the incoming clock frequency. This
option ensures that the FPGA remains in the Startup phase
of configuration until all clock outputs generated by the
DCM are stable. When all the DCMs with their
STARTUP_WAIT attribute set to TRUE assert the LOCKED
signal, then the FPGA completes its configuration process
and proceeds to user mode. The associated bitstream gen-
erator (BitGen) option LCK_cycle specifies one of the six
cycles in the Startup phase. The selected cycle defines the
point at which configuration halts until the all the LOCKED
outputs go High. Also see
Table 33: STARTUP_WAIT Attribute
Clocking Infrastructure
The Spartan-3E clocking infrastructure, shown in
provides a series of low-capacitance, low-skew interconnect
lines well-suited to carrying high-frequency signals through-
out the FPGA. The infrastructure also includes the clock
inputs and BUFGMUX clock buffers/multiplexers. The Xilinx
Place-and-Route (PAR) software automatically routes
high-fanout clock signals using these resources.
Clock Inputs
Clock pins accept external clock signals and connect directly
to DCMs and BUFGMUX elements. Each Spartan-3E FPGA
has:
•
•
•
Clock inputs optionally connect directly to DCMs using ded-
icated connections.
feed a specific DCM within a given Spartan-3E part number.
Different Spartan-3E FPGA densities have different num-
bers of DCMs.
Each clock input is also optionally a user-I/O pin and con-
nects to internal interconnect. Some clock pad pins are
input-only pins as indicated in
Data Sheet.
48
STARTUP_WAIT
16 Global Clock inputs (GCLK0 through GCLK15)
located along the top and bottom edges of the FPGA
8 Right-Half Clock inputs (RHCLK0 through RHCLK7)
located along the right edge
8 Left-Half Clock inputs (LHCLK0 through LHCLK7)
located along the left edge
Attribute
Table 35
Delays transition
from configuration
to user mode until
DCM locks to
input clock.
Description
Start-Up, page
shows the clock inputs that
Module 4
Table 33
of the Spartan-3E
TRUE, FALSE
91.
Values
Figure
optionally
www.xilinx.com
42,
Clock Buffers/Multiplexers
Clock Buffers/Multiplexers either drive clock input signals
directly onto a clock line (BUFG) or optionally provide a mul-
tiplexer to switch between two unrelated, possibly asynchro-
nous clock signals (BUFGMUX).
Each BUFGMUX element, shown in
multiplexer. The select line, S, chooses which of the two
inputs, I0 or I1, drives the BUFGMUX’s output signal, O, as
described in
other is glitch-less, and done in such a way that the output
High and Low times are never shorter than the shortest
High or Low time of either input clock.
Table 34: BUFGMUX Select Mechanism
The BUFG clock buffer primitive drives a single clock signal
onto the clock network and is essentially the same element
as a BUFGMUX, just without the clock select mechanism.
Similarly, the BUFGCE primitive creates an enabled clock
buffer using the BUFGMUX select mechanism.
The I0 and I1 inputs to an BUFGMUX element originate
from clock input pins, DCMs, or Double-Line interconnect,
as shown in
BUFGMUX elements distributed around the four edges of
the device. Clock signals from the four BUFGMUX elements
at the top edge and the four at the bottom edge are truly glo-
bal and connect to all clocking quadrants. The eight
left-edge BUFGMUX elements only connect to the two clock
quadrants in the left half of the device. Similarly, the eight
right-edge BUFGMUX elements only connect to the right
half of the device.
BUFGMUX elements are organized in pairs and share I0
and I1 connections with adjacent BUFGMUX elements from
a common clock switch matrix as shown in
example, the input on I0 of one BUFGMUX also a shared
input to I1 of the adjacent BUFGMUX.
The clock switch matrix for the left- and right-edge BUFG-
MUX elements receive signals from any of the three follow-
ing sources: an LHCLK or RHCLK pin as appropriate, a
Double-Line interconnect, or a DCM in the XC3S1200E and
XC3S1600E devices.
By contrast, the clock switch matrixes on the top and bottom
edges receive signals from any of the five following sources:
two GCLK pins, two DCM outputs, or one Double-Line inter-
connect.
Table 36
inputs and BUFGMUX elements. The four BUFGMUX ele-
ments on the top edge are paired together and share inputs
from the eight global clock inputs along the top edge. Each
indicates permissible connections between clock
S Input
Figure
Table
0
1
34. The switching from one clock to the
43. As shown in
Advance Product Specification
DS312-2 (v1.1) March 21, 2005
Figure
Figure
O Output
I0 Input
I1 Input
42, there are 24
43, is a 2-to-1
Figure
43. For
R