XC3S250E Xilinx, Inc., XC3S250E Datasheet - Page 78

• Manufacturer Part Number: XC3S250E
• Description: Spartan-3E FPGA Family
• Manufacturer: Xilinx, Inc.

In-System Programming Support
ally pre-programmed before it is mounted on the printed cir-
cuit board. In-system programming support is available
from some third-party PROM programmers using a socket
adapter with attached wires. To gain access to the SPI
Flash signals, drive the FPGA’s PROG_B input Low with an
open-drain driver. This action places all FPGA I/O pins,
including those attached to the SPI Flash, in high-imped-
ance (Hi-Z). If the HSWAP input is High, the I/Os have
pull-up resistors to the V
bank. The external programming hardware then has direct
access to the SPI Flash pins. The programming access
points are highlighted in the gray box in
Figure
Byte-Wide Peripheral Interface (BPI) Parallel
Flash Mode
In
(M[2:0] = <0:1:0> or <0:1:1>), a Spartan-3E FPGA config-
ures itself from an industry-standard parallel NOR Flash
PROM, as illustrated in
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
I
Recommend
open-drain
In a production application, the SPI Flash PROM is usu-
PROG_B
Byte-wide
driver
TMS
TDO
TCK
51, and
TDI
+2.5V
JTAG
R
Variant Select
Figure
SPI Mode
S
‘0’
‘0’
‘1’
‘1’
‘1’
P
Peripheral
54.
Figure
HSWAP
M2
M1
M0
VS2
VS1
VS0
TDI
TMS
TCK
PROG_B
CCO
Spartan-3E
VCCINT
FPGA
+1.2V
GND
input on their respective I/O
55. The FPGA generates up
Interface
VCCAUX
VCCO_0
VCCO_2
CSO_B
INIT_B
DONE
DOUT
Figure 54: Daisy-Chaining from SPI Flash Mode
CCLK
MOSI
TDO
DIN
VCCO_0
+3.3V
+2.5V
(BPI)
Figure
I
mode
www.xilinx.com
W
50,
‘1’
P
+2.5V
DATA_IN
DATA_OUT
SELECT
WR_PROTECT
HOLD
CLOCK
to a 24-bit address lines to access an attached parallel
Flash. Only 20 address lines are generated for Spartan-3E
FPGAs in the TQ144 package. The BPI mode is not avail-
able for Spartan-3E FPGAs in the VQ100 package.
The interface is designed for standard parallel NOR Flash
PROMs
byte-wide/halfword (x8/x16) PROMs. The interface does not
support halfword-only (x16) PROMs. The interface works
equally wells with other memories that use a similar inter-
face such as SRAM, NVRAM, EEPROM, EPROM, or
masked ROM but is primarily designed for Flash memory.
There is another type of Flash memory called NAND Flash,
which is commonly used in memory cards for digital cam-
eras, etc. Spartan-3E FPGAs do not configure directly from
NAND Flash memories.
The FPGA’s internal oscillator controls the interface timing
and the FPGA supplies the clock on the CCLK output pin.
However, the CCLK signal is not used in single FPGA appli-
cations. Similarly, the FPGA drives three pins Low during
configuration (LDC[2:0]) and one pin High during configura-
tion (HDC) to the PROM’s control inputs.
+3.3V
VCC
GND
Serial
Flash
+3.3V
SPI
and
Slave
Serial
Mode
P
‘1’
‘1’
‘1’
supports
HSWAP
M2
M1
M0
CCLK
DIN
TDI
PROG_B
TMS
TCK
Spartan-3E
VCCINT
FPGA
+1.2V
GND
both
VCCAUX
VCCO_0
VCCO_2
INIT_B
DOUT
DONE
TDO
Functional Description
byte-wide
VCCO_0
+3.3V
+2.5V
DS312-2_48_021405
(x8)
CCLK
DOUT
PROG_B
TCK
TMS
DONE
INIT_B
and
71