AD9887A Analog Devices, Inc., AD9887A Datasheet
AD9887A
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AD9887A Summary of contents
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... HDCP v1.0 protocol. Fabricated in an advanced CMOS process, the AD9887A is provided in a 160-lead, surface-mount, plastic MQFP and is specified over the 0°C to 70°C temperature range. The AD9887A is also available in an RoHS compliant package ...
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... AD9887A TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Analog Interface ........................................................................... 3 Digital Interface ............................................................................ 5 Absolute Maximum Ratings............................................................ 7 Explanation of Test Levels ........................................................... 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Pin Function Details—Pins Shared Between Digital and Analog Interfaces........................................................................ 11 Pin Function Details—Analog Interface ................................. 13 Pin Function Details— ...
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... Rev Page AD9887A AD9887AKS-170 Max Min Typ Max 8 +1.25/−1.0 ±0.8 +1.25/−1.0 +1.25/−1.0 +1.50/−1.0 ±1.4 ±1.0 ±2.25 ±2.5 ±2.75 Guaranteed 0.5 0.5 1.0 150 8.0 8 1.3 90 170 ...
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... Binary Binary 3.15 3.3 3.45 3.15 3.3 2.2 3.3 3.45 2.2 3.3 3.15 3.3 3.45 3.15 3.3 167 185 243 330 274 90 120 90 330 330 2 2 1.5 1 Rev Page AD9887AKS-170 Max Min Typ Max 2.6 0.8 0.8 −1.0 −1.0 1.0 1.0 3 2.4 0.4 0 Binary 3.45 3.15 3.3 3.45 3.45 2.2 3.3 3.45 3.45 3.15 3.3 3.45 230 55 60 360 345 390 120 90 120 330 2 1 ...
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... Full IV 3.15 3.3 3.45 Full IV 2.2 3.3 3.45 Full IV 3.15 3.3 3.45 25°C V 350 255° 255°C IV 130 VI 520 560 Full IV 360 Full IV 1.0 Full IV 2.5 Full IV 3.1 Full IV 5.4 AD9887A Unit Bits μ Clock period ...
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... Full L Output drive = low Full L Output drive = high; C =10 pF Full L Output drive = med Full L Output drive = low Full L Full Full 1 pixel/clock Full 2 pixels/clock Full Rev Page AD9887AKS Test Level Min Typ Max IV 1.2 IV 1.6 IV 2.3 IV 2.6 IV 3.0 IV 3.7 IV 1.4 IV 1 ...
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... Guaranteed by design and characterization testing 0 Parameter is a typical value only VI. 100% production tested at 25°C; guaranteed by design −25°C to +85°C and characterization testing. −65°C to +150°C 150°C 150°C ESD CAUTION Rev Page AD9887A ...
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... BLUE A<1> 29 BLUE A<0> GND 32 BLUE B<7> 33 BLUE B<6> 34 BLUE B<5> 35 BLUE B<4> 36 BLUE B<3> 37 BLUE B<2> 38 BLUE B<1> 39 BLUE B<0> CONNECT AD9887A TOP VIEW (Not to Scale) Figure 2. Pin Configuration Rev Page 120 MIDSC R 119 AIN R V 118 CLAMP V 117 D GND 116 115 V D 114 V D GND ...
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... Blue Channel Midscale Clamp Voltage Output Blue Channel Midscale Clamp Voltage Input External Filter Connection (Component of PLL) Main Power Supply Output Power Supply PLL Power Supply Ground Serial Port Data I/O Rev Page AD9887A Value Pin No. Interface 0 1.0 V 119 Analog 0 1.0 V 110 Analog 0 ...
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... AD9887A Pin Type Mnemonic 2-Wire Serial Interface SCL A0 A1 Data Outputs RED B[7:0] GREEN B[7:0] BLUE B[7:0] RED A[7:0] GREEN A[7:0] BLUE A[7:0] Data Clock Outputs DATACK DATACK Sync Detect S CDT Scan Function SCAN IN SCAN OUT SCAN CLK Digital Video Data Rx0+ Inputs Rx0− Rx1+ Rx1− ...
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... SCAN SCAN Data Clock for Scan Function CLK This pin clocks the data for the scan function. It controls both data input and output. Rev Page AD9887A pin is analog interface CDT pin switches to logic low under CDT pin, CLK ...
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... V) for compatibility. PV Clock Generator Power Supply D The most sensitive portion of the AD9887A is the clock generation circuitry. These pins provide power to the clock PLL and help the user design for optimal performance. The designer should provide noise-free power to these pins. ...
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... Coast polarity defaults power-up. External Clock Input (Optional) This pin can be used to provide an external clock to the AD9887A in place of the clock internally generated from HSYNC enabled by program- ming CKEXT to 1. When an external clock is used, all other internal functions, including the clock phase adjustment, operate normally ...
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... REFIN Reference Input The reference input accepts the master reference voltage for all AD9887A internal circuitry (1.25 V ± 10%). It can be driven directly by the REFOUT pin. Its high impedance presents a very light load to the reference source. This pin should always be bypassed to ground with a 0.1 μ ...
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... These signals are produced by the internal clock generator and are synchronous with the internal pixel sampling clock. When the AD9887A is operated in single-channel mode, the output frequency is equal to the pixel sampling frequency. When the AD9887A is operated in dual-channel mode, the clock frequency is half the pixel frequency ...
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... Data Enable DE Data Enable This pin outputs the state of data enable (DE). The AD9887A decodes DE from the incoming stream of data. The DE signal is high during active video and low when there is no active video. HDCP DDCSCL HDCP Slave Serial Port Data Clock For use in communicating with the HDCP-enabled DVI transmitter ...
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... V to 1.0 V p-p. Signals are typically brought onto the interface board via a DVI-I connector, a 15-lead D connector, or BNC connectors. The AD9887A should be located as close as is practical to the input connector. Signals should be routed via matched-impedance traces (normally 75 Ω) to the IC input pins. At this point, the signal should be resistively terminated (75 Ω ...
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... GAIN AND OFFSET CONTROL A block diagram of the gain and offset control integrated with each ADC is shown in Figure 5. The AD9887A can accommodate input signals of 0 1.0 V full scale. The full-scale range is set in three 8-bit registers (red gain, green gain, and blue gain). ...
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... Subtract these times from the total pixel period to determine the stable period. At higher pixel frequencies, both the total cycle time and stable pixel time are shorter. OFF 0V Rev Page AD9887A 47nF R AIN 47nF B AIN 47nF ...
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... Any jitter in the clock reduces the precision with which the sampling time can be determined and, thus, must be subtracted from the stable pixel time. The AD9887A clock generation circuit is designed to minimize jitter to less than 6% of the total pixel time in all operating modes, making its effect on valid sampling time negligible (see Figure 10) ...
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... Rev Page AD9887A Pixel Rate (MHz) VCORNGE CURRENT 25.175 00 011 31.500 00 100 31.500 00 100 36.000 00 101 36.000 00 101 40.000 01 011 50.000 01 011 49.500 01 011 56.250 01 100 65.000 01 101 75.000 10 011 78 ...
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... AD9887A ALTERNATE PIXEL SAMPLING MODE Logic 1 input on CKINV (Pin 94) inverts the nominal ADC clock. CKINV can be switched between frames to implement the alternate pixel sampling mode. This allows higher effective image resolution to be achieved at lower pixel rates, but with lower frame rates. ...
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... DATACK D OUTA HSOUT Three things happen to Hsync in the AD9887A. First, the polarity of the HSYNC input is determined and, thus, has a known output polarity. The known output polarity can be programmed either active high or active low (Register 0x04, Bit 4). Second, HSOUT is aligned with DATACK and data outputs. Third, the duration of HSOUT (in pixel clocks) is set via Register 0x07 ...
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... AD9887A RGB HSYNC PXCK HS ADCCK DATACK D OUTA HSOUT Figure 19. Single-Channel Mode, Alternate Pixel Sampling (Even Pixels, Analog Interface) RGB HSYNC PXCK HS ADCCK DATACK D OUTA HSOUT Figure 20. Single-Channel Mode, Alternate Pixel Sampling (Odd Pixels, Analog Interface) ...
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... Figure 23. Dual-Channel Mode, Interleaved Outputs, Alternate Pixel Sampling (Even Pixels, Analog Interface), Outphase = 0 RGB HSYNC PXCK HS 8-PIPE DELAY ADCCK DATACK D OUTA D OUTB HSOUT Figure 24. Dual-Channel Mode, Interleaved Outputs, Alternate Pixel Sampling (Odd Pixels, Analog Interface), Outphase = Rev Page AD9887A ...
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... AD9887A RGB IN HSYNC PXCK HS ADCCK DATACK D OUTA D OUTB HSOUT Figure 25. Dual-Channel Mode, Parallel Outputs, Alternate Pixel Sampling (Even Pixels, Analog Interface), Outphase = 0 RGB HSYNC PXCK HS ADCCK DATACK D OUTA D OUTB HSOUT Figure 26. Dual-Channel Mode, Parallel Outputs, Alternate Pixel Sampling (Odd Pixels, Analog Interface), Outphase = 0 ...
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... When the analog interface is being used, most of the digital interface circuitry can be powered down and vice versa. This helps to minimize the total power CLK dissipation of the AD9887A. In addition, if neither interface has ACTIVE 10kΩ activity on it, both interfaces should be powered down. ...
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... The scan function is intended as a pseudo JTAG function for the manufacturing test of the board. The ordinary operation of the AD9887A is disabled during scanning. To enable the scan function, set Register 0x14, Bit scan data to all 48 digital outputs, apply 48 serial bits of data and 48 clock cycles (typically 5 MHz, ...
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... DVI transmitter enables HDCP through the DDC port. The AD9887A then decodes the DVI stream using information provided by the transmitter, HDCP keys, and KSV. The AD9887A allows the MDA and MCL pins to be three-state, using the MDA/MCL three-state bit (Register 0x1B, Bit 7) in the configuration registers ...
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... CONNECTOR DDC CLOCK DDC DATA DVI-VCC 3.3V 3.3V PULL-UP 5kΩ 5kΩ RESISTORS 150Ω DDCSCL SERIES AD9887A RESISTOR DDCSDA D S 3.3V RESISTOR Figure 32. HDCP Implementation Using the AD9887A Rev Page 3.3V PULL-UP 2kΩ 2kΩ RESISTORS MCL SCL EEPROM MDA SDA 10kΩ PULL-UP ...
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... Figure 38. One Pixel per Clock (DATACK Not Inverted FIRST PIXEL THIRD PIXEL SECOND PIXEL FOURTH PIXEL Figure 39. Two Pixels per Clock FIRST PIXEL THIRD PIXEL SECOND PIXEL FOURTH PIXEL Figure 40. Two Pixels per Clock (DATACK Inverted) AD9887A FOURTH PIXEL PIXEL ...
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... AD9887A 2-WIRE SERIAL REGISTER MAP The AD9887A is initialized and controlled by a set of registers that determine the operating modes. An external controller is used to write and read the control registers through the 2-line serial interface port. Table 9. Control Register Map Read and Write, or Default ...
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... Bit 7 = Logic 1 in Register 0x11). Bit 3—Active Vsync Override. If set to Logic 1, the user can select the Vsync to be used via Bit 2. If set to Logic 0, the active interface is selected via Bit 1 in Register 0x11. Rev Page AD9887A pin. CDT ...
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... AD9887A Read and Write, or Default Address Read Only Bits Value *****0** ******0* *******1 0x13 R/W 7:0 00100000 0x14 R/W 7:0 ***1**** ****0*** *****0** ******0* *******0 0x15 RO 7:5 0******* *0****** **0***** 0x16 R/W 7:2 10111*** *****1** 0x17 R/W 7:0 00000000 0x18 R/W 7:0 00000000 0x19 R/W 7:0 00000000 0x1A R/W 7:0 11111111 0x1B R/W 7:0 00000000 0x1C R/W 7:0 00000*** *****1** ******1* *******1 0x1D RO 7:0 *_***** 0x1E R/W 7:0 11111111 0x1F R/W 7:0 10000100 0x20 ...
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... R/W 7:0 11111111 0x27 00001111 1 The AD9887A only updates the PLL divide ratio when the LSBs are written to Register 0x02. 2-WIRE SERIAL CONTROL REGISTER DETAILS Chip Identification 0x00 7:0 Chip Revision Bit 7 through Bit 4 represent functional revisions to the analog interface. Changes in these bits generally indicate that software and/or hardware changes are required for the chip to work properly ...
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... The leading edge of the Hsync output is triggered by the internally generated, phase-adjusted PLL feedback clock. The AD9887A counts the number of pixel clock cycles set in this register. This triggers the trailing edge of the Hsync output, which is also phase adjusted. Input Gain ...
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... One bit that inverts the polarity of the VSYNC output. Table 16 shows the effect of this option. Table 16. VSYNC Output Polarity Settings Setting VSYNC Output 0 Invert 1 No invert The default setting for this register is 1. This option works on both the analog and digital interfaces. Rev Page AD9887A ...
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... AD9887A 0x0F 7 HSYNC Input Polarity A bit that must be set to indicate the polarity of the Hsync signal that is applied to the PLL HSYNC input. Table 17. HSYNC Input Polarity (HSPOL) Settings HSPOL Function 0 Active low 1 Active high Active low is the traditional negative-going Hsync pulse. All timing is based on the leading edge of Hsync, which is the falling edge ...
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... This pin controls the polarity of the sync detect output pin (Pin 136). Table 29. Sync Detect Polarity Settings Polarity Function 0 Activity = Logic 1 output 1 Activity = Logic 0 output The default for this register is 0. This option works on both the analog and digital interfaces. Rev Page AD9887A ...
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... AD9887A SYNC Detection/Active Interface Control 0x11 7 Analog Interface HSYNC Detect This bit is used to indicate when activity is detected on the HSYNC input pin (Pin 82). If HSYNC is held high or low, activity is not detected. Table 30. Analog Interface HSYNC Detection Results Detect Function 0 No activity detected ...
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... Autodetermines the active Vsync Override, Bit 2 determines the active Vsync The default for this register is 0. Active Vsync Select Result VSYNC input Sync separator output The default for this register is 0. Coast Select Result COAST input pin Vsync (see above text) AD9887A ...
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... The default for this register is 32. Control Bits 0x14 2 Scan Enable This register is used to enable the scan function. When this function is enabled, data can be loaded into the AD9887A outputs serially. The scan function utilizes three pins: SCAN , SCAN , and SCAN IN OUT are described in the Scan Function section ...
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... Pin 49 = CTL3 signal The default setting is 0. 0x20 5 Analog Input Bandwidth Control This bit controls the analog input bandwidth. Table 56. Analog Input Bandwidth Control Select Input Bandwidth 0 High analog input bandwidth 1 Low analog input bandwidth The default setting 0. Rev Page AD9887A ...
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... AD9887A 0x20 4 MDA/MCL Three-State This bit allows the MDA/MCL lines to be three-stated so that the HDCP key EEPROM can be programmed in-circuit. Table 57. MDA/MCL Three-State Select MDA/MCL Output 1 Normal operation 0 MDA/MCL set to three-state The default setting is 0. 0x20 3 External Oscillator This bit allows use of either the internal oscillator or an external one supplied on the A0 pin ...
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... Any base address higher than 0x1D does not produce an acknowledge signal. Data is read from the control registers of the AD9887A in a similar manner. Reading requires two data transfer operations. The base address must be written with the R/ W bit of the slave address byte low to set up a sequential read operation ...
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... AD9887A SDA t BUFF t DHO t STAH SCL SDA SCL t t DSU STASU t DAL t DAH Figure 41. Serial Port R/ W Timing BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 Figure 42. Serial Interface—Typical Byte Transfer Rev Page STOSU BIT 0 ACK ...
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... Bit 0x12, Bit 0x11, Bit 3 0 and 7 1 Rev Page AD9887A Result Pass Hsync Pass sync-on-green Pass coast Pass Vsync Pass Vsync Pass sync separator signals Pass digital interface signals Pass analog interface signals ...
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... Hsync signal. Therefore, it rejects any signal shorter than a threshold value, which is somewhere in the range between an Hsync pulse width and a Vsync pulse width. The sync separator on the AD9887A is simply an 8-bit digital counter with a 5 MHz clock. It works independently of the polarity of the composite sync signal. (Polarities are determined elsewhere on the chip ...
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... In some cases, using separate ground planes is unavoidable. For these cases recommended to place at least a single ground plane under the AD9887A. The location of the split should be at the receiver of the digital outputs. For these cases even more important to place components wisely because the current loops are much longer, and current takes the path of least resistance ...
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... Adding a series resistor with a value of 22 Ω to 100 Ω can suppress reflections, reduce EMI, and reduce the current spikes inside of the AD9887A. However Ω traces are used on the PCB, the data outputs should not need these resistors Ω resistor on the DATACK output should provide good impedance matching that further reduces reflections ...
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... VIEW A ROTATED 90° CCW ORDERING GUIDE Model Max Speed (MHz) Analog AD9887AKS-100 100 1 AD9887AKSZ-100 100 AD9887AKS-140 140 1 AD9887AKSZ-140 140 AD9887AKS-170 170 AD9887AKSZ-170 1 170 AD9887A/PCB RoHS Compliant Part. 31.45 4.10 31.20 SQ 1.03 MAX 30.95 0.88 0.73 120 121 SEATING PLANE TOP VIEW (PINS DOWN) VIEW A 10° PIN 1 6° ...
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... AD9887A NOTES ©2003–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02838-0-3/07(B) T Rev Page ...