AD9887A Analog Devices, Inc., AD9887A Datasheet - Page 23

• Manufacturer Part Number: AD9887A
• Description: Dual Interface For Flat Panel Displays
• Manufacturer: Analog Devices, Inc.

TIMING—ANALOG INTERFACE
The timing diagrams (Figure 18 through Figure 27) show the
operation of the AD9887A analog interface in all clock modes.
The part establishes timing by sending the pixel corresponding
with the leading edge of Hsync to Data Port A. In dual-channel
mode, the next sample is sent to Data Port B. Subsequent samples
are alternated between the A and B data ports. In single-channel
mode, data is only sent to Data Port A, and Data Port B is placed
in a high impedance state.
The output data clock signal is created so that its rising edge
always occurs between transitions of Data Port A and can be
used to latch the output data externally.
Hsync Timing
Horizontal sync is processed in the AD9887A to eliminate
ambiguity in the timing of the leading edge with respect to the
phase-delayed pixel clock and data.
The HSYNC input is used as a reference to generate the pixel
sampling clock. The sampling phase can be adjusted with respect
to Hsync through a full 360° in 32 steps via the phase adjust
register to optimize the pixel sampling time. Display systems
use Hsync to align memory and display write cycles; therefore,
it is important to have a stable timing relationship between the
HSYNC output (HSOUT) and data clock (DATACK).
ANY OUTPUT
(OUTPUT)
DATACK
SIGNAL
PXCK
t
SKEW
DATACK
ADCCK
HSYNC
HSOUT
RGB
Figure 17. Analog Output Timing
D
PXCK
OUTA
HS
IN
DATA OUT
P0
P1
P2
t
7-PIPE DELAY
PER
P3
t
DCYCLE
Figure 18. Single-Channel Mode (Analog Interface)
P4
P5
Rev. B | Page 23 of 52
P6
P7
D1
Three things happen to Hsync in the AD9887A. First, the polarity
of the HSYNC input is determined and, thus, has a known output
polarity. The known output polarity can be programmed either
active high or active low (Register 0x04, Bit 4). Second, HSOUT
is aligned with DATACK and data outputs. Third, the duration
of HSOUT (in pixel clocks) is set via Register 0x07. Use the
HSOUT signal to drive the rest of the display system.
Coast Timing
In most computer systems, the Hsync signal is provided
continuously on a dedicated wire. In these systems, the coast
input and function are unnecessary and should not be used.
In some systems, however, Hsync is disturbed during the vertical
sync (Vsync) period, and sometimes Hsync pulses disappear.
In other systems, such as those that use composite sync (Csync)
signals or those that embed sync-on-green (SOG), Hsync includes
equalization pulses or other distortions during Vsync. To avoid
upsetting the clock generator during Vsync, it is important to
ignore these distortions. If the pixel clock PLL sees extraneous
pulses, it attempts to lock on to this new frequency and changes
frequency by the end of the Vsync period. It then requires a few
lines of correct Hsync timing to recover at the beginning of a new
frame, resulting in a tearing of the image at the top of the display.
The coast input is provided to eliminate this problem. It is an
asynchronous input that disables the PLL input and holds the
clock at its current frequency. The PLL can operate in this manner
for several lines without significant frequency drift.
Coast can be provided by the graphics controller, or it can be
internally generated by the AD9887A sync processing engine.
D2
D3
D4
D5
D6
AD9887A