AD9887A Analog Devices, Inc., AD9887A Datasheet - Page 11

• Manufacturer Part Number: AD9887A
• Description: Dual Interface For Flat Panel Displays
• Manufacturer: Analog Devices, Inc.

PIN FUNCTION DETAILS—PINS SHARED BETWEEN DIGITAL AND ANALOG INTERFACES
Sync Outputs
HSOUT
VSOUT
2-Wire Serial Port
SDA
SCL
A0
A1
Data Outputs
RED A
RED B
GREEN A Data Output, Green Channel, Port A/Even
GREEN B Data Output, Green Channel, Port B/Odd
BLUE A
BLUE B
Serial Port Data I/O
Data Output, Red Channel, Port A/Even
Data Output, Red Channel, Port B/Odd
Horizontal Sync Output
The horizontal sync output is a reconstructed
version of the video Hsync, phase-aligned with
DATACK. The polarity of this output can be
controlled via a serial bus bit. In analog interface
mode, the placement and duration are variable. In
digital interface mode, the placement and duration
are set by the graphics transmitter.
Vertical Sync Output
The Vsync is separated from a composite signal or
a direct pass-through of the Vsync input. The polarity
of this output can be controlled via a serial bus bit.
The placement and duration in all modes are set by
the graphics transmitter.
Serial Port Data Clock
Serial Port Address Input 1
Serial Port Address Input 2
For a full description of the 2-wire serial register
and how it works, see the 2-Wire Serial Control
Port section.
Data Output, Blue Channel, Port A/Even
Data Output, Blue Channel, Port B/Odd
These outputs are the main data outputs. Bit 7 is the
MSB. These outputs are shared between the two
interfaces.
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Data Clock Outputs
DATACK Data Output Clock
DATACK Data Output Clock Complement
Sync Detect
S
Scan Function
SCAN
SCAN
SCAN
CDT
OUT
CLK
IN
Like the data outputs, the data clock outputs are
shared between the two interfaces. They also behave
differently, depending on which interface is active.
See the Theory of Operation and Design Guide—
Analog Interface and the Theory of Operation—
Digital Interface sections for details on how these
pins behave.
Chip Active/Inactive Detect Output
The logic for the S
HSYNC detection or digital interface DE detection.
Therefore, the S
two conditions: when neither interface is active, or
when the chip is in full power-down mode. The data
outputs are automatically set to three-state when
S
identify periods of inactivity.
Data Input for Scan Function
By using the scan function, 48 bits of data can be
loaded into the data outputs. Data is input serially
through this pin, clocked with the SCAN
and comes through the outputs as parallel words.
This function is useful for loading known data into
a graphics controller chip for testing purposes.
Data Output for Scan Function
The data input serially into the SCAN
be read through this pin. Data is read on a FIFO
basis and is clocked via the SCAN
Data Clock for Scan Function
This pin clocks the data for the scan function.
It controls both data input and output.
CDT
is low. This pin can be read by a controller to
CDT
CDT
pin switches to logic low under
pin is analog interface
CLK
pin.
IN
AD9887A
register can
CLK
pin,