MT312 Zarlink Semiconductor, MT312 Datasheet - Page 13

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

MT312
Design Manual
Error
Count
VIT_ERRCNT[23:0]
0
0
VIT_ERRPER[23:0]
Data Bits
IRQ
Figure 4 - Viterbi error count measurement
Figure 4 shows the bit errors rising until the maximum programmed value of VIT_ERRPER[23:0] is reached, when
an interrupt is generated on the IRQ line to advise the host microprocessor that a new value of bit error count has
been loaded into the VIT_ERRCNT [23:0] register. The IRQ line will go high when the IE_FEC register is read by
the host microprocessor. The error count may be expressed as a ratio:
VIT_ERRCNT[23:0]
VIT_ERRPER[23:0]*4
2.4.1.1
Viterbi error count coarse indication
To assist in the process of aligning the receiver dish aerial, a coarse indication of the number of bit errors being
received can be provided by monitoring the STATUS line with the following set up conditions.
The frequency of the output waveform will be a function of the bit error count (triggering the maximum value
programmed into the VIT_MAXERR[7:0] register and the dish alignment on the satellite. This VIT_MAXERR mode
is enabled by setting the FEC_STAT_EN register bit-0. Figure 5 below shows the bit errors rising to the maximum
value programmed and triggering a change of state on the STATUS line.
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Zarlink Semiconductor Inc.