MT312 Zarlink Semiconductor, MT312 Datasheet - Page 37

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

6.3
6.3.1
Note that the most significant four bits are not reset on read. The least significant four bits are interrupt bits which
are reset when the register is read. Interrupts indicate events in history. The interrupts may be enabled to drive the
IRQ pin 57 by setting required bit(s) in the DISEQC2_CTRL1 register 121, see page 35.
bit-7-4:
bit-3:
bit-2:
bit-1:
bit-0:
DISEQC2_INT
NAME
DiSEqC Control Read Registers
DISEQC2 Interrupt Indicators register 118 (R)
Bits-7-4 denote the following number of bytes received:
Silent period exceeds 176 ms interrupt (reset on read)
Receive error interrupt (reset on read).
End of message interrupt (reset on read).
Hence this is the number of bytes that would be in the FIFO BUFFER if this buffer had unlimited
capacity. Since the size of this buffer is only 8 bytes, if the above difference, given by bits 7-4, exceeds
eight, that indicates buffer overflow.
The host may enable interrupts bit-1 and bit-3. Then when an interrupt is received, the host may read
the DISEQC2_INT register. Then if bit-3 is one and bit-1 is 0, this indicates there has been a continuous
period 176ms of silence since the end of the transmission. If the host is expecting a reply, then this
silence may be taken to signify a hardware fault in the system.
There is a 5-bit number in the DISEQC2_STATUS BYTE which indicates the length of a continuous
period of silence up to the read time, in multiples of 16 ms.
Bit-2 indicates an error in the received message. This does not refer to a parity error. It indicates that a
bit has been lost due to excessive noise or interference in the return channel. This is identified within
MT312 by the occurrence of an excessively long tone or silence period within a byte.
Bit-1 indicates a new message has been received. The end of a message is identified by a silent period
of about 6 ms following a byte. The end-of-message interrupt bit makes it easier for the host processor
to read DiSEqC™ data from MT312. Instead of reading a byte at a time, it can read the message as a
whole.
It is important to note that MT312 does not stop accepting bytes after setting end-of-message interrupt.
It will receive new messages, if any, whilst the current message is being read by the host. Since the
2-wire bus read rate is higher than the byte receive rate, there is no reason for FIFO buffer overflow.
After every received message there will be an interrupt.
End of byte interrupt (reset on read).
Bit-0 is set when a new byte is received. The host may wish to ignore byte interrupts and opt to read
received messages, as described below.
It is important to note that MT312 does not stop accepting bytes after setting end-of-message interrupt.
It will receive new messages, if any, whilst the current message is being read by the host. Since 2-wire
bus read rate is higher than the byte receive rate, there is no reason for FIFO buffer overflow.
After every received message there will be an interrupt.
ADR
118
bit-7
bit-7-4 = (Number of bytes received - Number of bytes read)
bit-6
bit-5
Zarlink Semiconductor Inc.
DISEQC2_INT[7:0]
bit-4
MT312
37
bit-3
bit-2
bit-1
bit-0
R
Def hex
00
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