MT312 Zarlink Semiconductor, MT312 Datasheet - Page 55

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MT312

Manufacturer Part Number
MT312
Description
Satellite Channel Decoder
Manufacturer
Zarlink Semiconductor
Datasheet

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9.2
9.2.1
bits 7-0:
Note:
9.2.2
AGC[13:0]:
To avoid having too large a number, the following formula extracts a number less than 1024:
Approximate input level = AGC[13-4].
ERR_DB[9:0]: The ERR_DB is the difference between the expected signal level defined by AGC_REF and
The way H/M/L registers work within the QPSK block is as follows. When the H register is read, the 24-bit value is
copied into a shadow register. Reading the M and L registers is optional after this. It is NOT an option to read M and
L (or just L of a 24 or 16-bit register) without reading H. The safest solution is to read H/M/L in that order.
SIG_LEVEL
AGC M
AGC H
AGC L
NAME
NAME
Automatic gain control read registers
Measured signal level at MT312 input register 19 (R)
Measured AGC feed back value registers 108 - 110 (R)
ADR
SIG_LEVEL[7:0]:
the signal level is measured at the output of the ADC before any digital filtering takes place. Hence the
reading includes all noise and other signal channels passed by the SAW or baseband filter.
108
109
110
front end. Reading the bytes does NOT reset the value.This measurement can be used to provide
an indication of the signal level at the input to the tuner.
received signal level. This is in a non-linear logarithmic scale (hence the notation DB).
These two registers provide a measurement of the AGC error feed back value by the MT312 to the
ADR
19
bit-7
AGC[5:0] - Front end AGC (low byte)
bit-7
bit-6
ERR_DB[7:0] - Error difference (low byte)
AGC[13:6] - Front end AGC (high byte)
SIG_LEVEL[7:0] - Signal level at MT312 input
bit-6
is controlling the signal level, there is a direct relationship between SIG_LEVEL
and AGC_REF: SIG_LEVEL * 8 = AGC_REF
This register provides a measurement of the MT312 input signal level. When AGC
bit-5
bit-5
bit-4
Zarlink Semiconductor Inc.
bit-4
bit-3
MT312
bit-3
55
bit-2
bit-2
ERR_DB[9:8]
bit-1
bit-1
bit-0
bit-0
R
R
R
R
hex
Def
00
00
00
hex
Def
00
Design Manual

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