vsc870 Vitesse Semiconductor Corp, vsc870 Datasheet - Page 24

• Manufacturer Part Number: vsc870
• Description: High Performance Serial Backplane Transceiver
• Manufacturer: Vitesse Semiconductor Corp

Page 24
High Performance Serial
Backplane Transceiver
2.4 Receiver Operation
section 2.2 “Data Encoding Format” for the coding of these signals. If the receive word is an IDLE word, the RXWA
signal is set LOW so the FIFO can use this signal to filter out these null data words. If the receiver detects an ACK for
the connection request on the transmit side, the ACK/RCLK signal is asserted for one word clock. The RXOUT data
bus and RXTYP outputs can be tristated by asserting RXEN. CRQ words, header words, IDLE words and data words
are sent to the receiving port card. A functional timing diagram for a typical receiver operation is shown in the
following figure. See Application Note 31 for more detailed information.
2.5 Flow Control Channel
supports two logic states that are sent from the receiving port card back to the transmitting port card. The flow
control channel is time shared with the signaling between the switch chip and the transceiver for acknowledgment
and response bits for Multi Queue connection requests. Therefore, it can only guarantee to pass the state information
from the RTR pin at the receiving port card through the switch and to the REN pin at the transmitting port card. The
REN pin is also shared between the flow control channel and the transceiver’s connection request retransmission
logic. To apply backpressure to the transmitting port card, the RTR signal should be set LOW. An application for this
flow control channel is to prevent the FIFO on the receiving side from overflowing. In this case, the
The transceiver can support a back pressure mechanism by providing a flow control channel. This channel
In Packet Mode, the receiver examines incoming words and generates the data type signals accordingly. Refer to
TXTYP[1:0]
RXTYP[1:0]
TXIN[31:0]
RXIN[31:0]
RTM/TCLK
ACK/RCLK
Figure 8: Multi Queue Transmitter Functional Timing (with early arbitration)
WCLK
WCLK
RXWA
REN
CRQ
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
HDR
3
2
Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]
Figure 9: Receive Channel Functional Timing
DX
D0
1
1
Minimum of 9 clock cycles
VITESSE
SEMICONDUCTOR CORPORATION
DX
D1
D2
Last 13 words of current data packet
DX
D3
Internet: www.vitesse.com
DX
D4
DX
DX
DN
P0
CRQ
DX
P1
3
DX HDR
idle
P2
0
idle
P3
HDR D0
Time to select data queue
2
and reconfigure switch
D0
1
D1
D1
D2
VSC870
Data Sheet
G52190-0, Rev 4.1
01/05/01