vsc870 Vitesse Semiconductor Corp, vsc870 Datasheet - Page 28

• Manufacturer Part Number: vsc870
• Description: High Performance Serial Backplane Transceiver
• Manufacturer: Vitesse Semiconductor Corp

Page 28
High Performance Serial
Backplane Transceiver
words, are passed through the switch matrix. In this case, command words such as IDLEs must be used periodically
for checking the link integrity. At the last word of a cell clock period, if the user sends an IDLE word, bits B[1:0] of
the IDLE word are set to ‘11’ to embed the cell clock information. The switch will flag a cell sync error if this IDLE
word does not contain a cell clock. The transmitter can force an IDLE word at the end of any given cell period by
setting the signal TXEN LOW.
3.4 Receiver Operation
timing diagram. If the received words are data, the overhead bits RXTYP[1:0] will be set to 01, 10 or 11. If the
received word is a command word, RXTYP[1:0] will be set to 00. If the received word is an IDLE word, the signal
RXWA will also go LOW. If the transceiver receives an IDLE word during the last word of the cell clock period
without B[1:0] = 11, a cell sync error condition will be flagged, and the signal TXOK will pulse HIGH.
At the receiving side, the transceiver examines incoming words and overhead bits. Figure 12 shows the receiver
TXTYP[1:0]
RXTYP[1:0]
RTM/TCLK
TXIN[31:0]
RXIN[31:0]
WCLK
WCLK
RCLK
Figure 11: Cell Mode Transmitter Functional Timing at Port Card
Figure 12: Cell Mode Receiver Functional Timing at Port Card
D0
D0
1 or 2 or 3
1 or 2 or 3
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
D1
D1
Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]
VITESSE
D2
D2
SEMICONDUCTOR CORPORATION
User defined cell period
User defined cell period
D3
D3
D4
D4
Internet: www.vitesse.com
D5
D5
D6
D6
DN
DN
D0
D0
D1
D1
D2
D2
D3
D3
VSC870
Data Sheet
D4
D4
G52190-0, Rev 4.1
01/05/01