vsc870 Vitesse Semiconductor Corp, vsc870 Datasheet - Page 5

• Manufacturer Part Number: vsc870
• Description: High Performance Serial Backplane Transceiver
• Manufacturer: Vitesse Semiconductor Corp

Data Sheet
VSC870
G52190-0, Rev 4.1
01/05/01
FACLPBK
REFCLK
TESTEN
DLYEN/
Symbol
CCKIN
VSCTE
WCLK
RESET
LTIME
VDDA
VSSA
Delay Enable/Cell Clock
NOR Chain Test Enable
Local Reference Clock
CMU Power Supply
Facility Loopback
Loop Time Mode
Scan Test Enable
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
CMU Ground
Word Clock
Name
Reset
Input
Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]
VITESSE
SEMICONDUCTOR CORPORATION
I/O
O
P
P
I
I
I
I
I
I
I
Internet: www.vitesse.com
62.5MHz
62.5MHz
62.5Mb/s
<1MHz
<1MHz
<1MHz
<1MHz
<1MHz
Freq
Type
3.3V
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
0V
If BYPASS is LOW, this signal can be set HIGH to enable
REN delay mode. In Cell Mode, DLYEN/CCKIN can be
used as an input for cell clock alignment.
When this signal is HIGH, the serial input is looped back
to the serial output. It should be normally set LOW.
The word clock is a delayed version of the WSIN signal.
A 62.5 MHz local reference clock that is used to keep the
CRU close to the incoming bit clock frequency before the
alignment process begins. Is also used as a reference
clock for the CMU.
Global chip reset (active HIGH).
When TESTEN is HIGH, the REFCLK is used in place
of the bit clock for low speed testing. Used for ATE
testing only. Set to logic LOW during normal operation.
LTIME is set HIGH to use the recovered bit clock for the
transmit side.
Used for ATE testing of the parametric NOR chain in the
I/O frame. Set to logic LOW during normal operation.
Clean power supply for CMU
Clean ground for CMU
Description
High Performance Serial
Backplane Transceiver
Page 5