tsc251g1dxxx-l12ced ATMEL Corporation, tsc251g1dxxx-l12ced Datasheet - Page 21

• Manufacturer Part Number: tsc251g1dxxx-l12ced
• Description: 8/16-bit Microcontroller With Serial Communication Interfaces - 32kbytes Rom
• Manufacturer: ATMEL Corporation

Instruction Set
Summary
Notation for Instruction
Operands
4135F–8051–11/06
This section contains tables that summarize the instruction set. For each instruction
there is a short description, its length in bytes, and its execution time in states (one state
time is equal to two system clock cycles). There are two concurrent processes limiting
the effective instruction throughput:
•
•
Table 20 to Table 32 assume code executing from on-chip memory, then the CPU is
fetching 16-bit at a time and this is never limiting the execution speed.
If the code is fetched from external memory, a pre-fetch queue will store instructions
ahead of execution to optimize the memory bandwidth usage when slower instructions
are executed. However, the effective speed may be limited depending on the average
size of instructions (for the considered section of the program flow). The maximum aver-
age instruction throughput is provided by Table 14 depending on the external memory
configuration (from Page Mode to Non-Page Mode and the maximum number of wait
states). If the average size of instructions is not an integer, the maximum effective
throughput is found by pondering the number of states for the neighbor integer values.
Table 14. Minimum Number of States per Instruction for given Average Sizes
If the average execution time of the considered instructions is larger than the number of
states given by Table 14, this larger value will prevail as the limiting factor. Otherwise,
the value from Table 14 must be taken. This is providing a fair estimation of the execu-
tion speed but only the actual code execution can provide the final value.
Table 15 to Table 19 provide notation for Instruction Operands.
Table 15. Notation for Direct Addressing
Direct
Address
dir8
dir16
of Instructions
Average size
Instruction Fetch
Instruction Execution
(bytes)
1
2
3
4
5
Description
A direct 8-bit address. This can be a memory address (00h-7Fh) or a
SFR address (80h-FFh). It is a byte (default), word or double word
depending on the other operand.
A 16-bit memory address (00:0000h-00:FFFFh) used in direct
addressing.
Page Mode
(states)
1
2
3
4
5
0 Wait
State
10
2
4
6
8
1 Wait
State
12
15
3
6
9
Non-page Mode (states)
2 Wait States 3 Wait States 4 Wait States
AT/TSC8x251G2D
12
16
20
4
8
10
15
20
25
5
C251
3
3
12
18
24
30
6
C51
3
–
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