tsc251g1dxxx-l12ced ATMEL Corporation, tsc251g1dxxx-l12ced Datasheet - Page 28
tsc251g1dxxx-l12ced
Manufacturer Part Number
tsc251g1dxxx-l12ced
Description
8/16-bit Microcontroller With Serial Communication Interfaces - 32kbytes Rom
Manufacturer
ATMEL Corporation
Datasheet
1.TSC251G1DXXX-L12CED.pdf
(77 pages)
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Notes:
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1. Logical instructions that affect a bit are in Table 27.
2. A shaded cell denotes an instruction in the C51 Architecture.
3. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. If this instruction addresses an I/O Port (Px, x = 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
5. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
6. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).
AT/TSC8x251G2D
Table 23. Summary of Logical Instructions (2/2)
Note:
Shift Left LogicalSLL <dest><dest>
Shift Right ArithmeticSRA <dest><dest>
Shift Right LogicalSRL <dest><dest>
SwapSWAP AA
Mnemonic
SLL
SRA
SRL
SWAP
<dest>
(CY) ← <dest>
<dest>
(CY) ← <dest>
<dest>
(CY) ← <dest>
1. A shaded cell denotes an instruction in the C51 Architecture.
n+1
n-1
n-1
← <dest>
← <dest>
← <dest>
3:0
<dest>,
<src>
Rm
WRj
Rm
WRj
Rm
WRj
A
A
msb
0
0
7:4
n
n
n
(1)
, n = msb..1
, n = msb..1
, n = 0..msb-1
Comments
Shift byte register left through the
MSB
Shift word register left through the
MSB
Shift byte register right
Shift word register right
Shift byte register left
Shift word register left
Swap nibbles within ACC
0
← 0
msb
msb
← 0
← <dest>
msb
Bytes
Binary Mode
3
3
3
3
3
3
1
States
2
2
2
2
2
2
2
4135F–8051–11/06
Bytes
Source Mode
2
2
2
2
2
2
1
States
1
1
1
1
1
1
2
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