adv7150 Analog Devices, Inc., adv7150 Datasheet

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... The ADV7150 integrates a number of graphic functions onto one device allowing 24-bit direct True-Color op- eration at the maximum screen update rate of 220 MHz. The ADV7150 implements 30-bit True Color in 24-bit frame buffer designs. The part also supports other modes, including 15-bit < 1.0 C/W JC True Color and 8-bit Pseudo or Indexed Color ...

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... ADV7150–SPECIFICATIONS pF); IOR, IOG, IOB = GND. All specifications T L Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity Gray Scale Error Coding DIGITAL INPUTS (Excluding CLOCK, CLOCK) Input High Voltage, V INH Input Low Voltage, V INL Input Current, I ...

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... ADV7150 . IOR, IOG, IOB ( Conditions/Comments MHz max Pixel CLOCK Rate ns min Pixel CLOCK Cycle Time ns min Pixel CLOCK High Time ns min Pixel CLOCK Low Time ns max Pixel CLOCK to LOADOUT Delay ...

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... ADV7150 NOTES 1 TTL input values are volts, with input rise/fall times V –0 –1.8 V, with input rise/fall times AA AA puts. Analog output load 10 pF. Databus (D0–D9) loaded as shown in Figure 1. Digital output load for LOADOUT, PRGCKOUT, SCKOUT, I SYNCOUT 30 pF for all versions. ...

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... Figure 5. Pixel Input to Analog Output Pipeline with Maximum LOADOUT to LOADIN Delay (4:1 Multiplex Mode) REV N+2 N N+2 N N–1 N– N+1 N+1 N+1 N+1 N N+1 N+1 N+2 N N+1 N+1 N+2 N N–1 N–1 N– N+1 N+1 N+1 N+1 N+2 –5– ADV7150 C D N+2 N+2 N+2 – N+2 N+2 N+2 ...

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... ADV7150 CLOCK LOADOUT LOADIN PIXEL INPUT N+1 N+1 DATA* IOR, IOR ANALOG IOG, IOG OUTPUT IOB, IOB DATA I PLL, SYNCOUT *INCLUDES PIXEL DATA (R0–R7, G0–G7, B0–B7); PALETTE SELECT INPUTS (PS0–PS1); BLANK; SYNC Figure 6. Pixel Input to Analog Output Pipeline with Minimum LOADOUT to LOADIN Delay (2:1 Multiplex Mode) ...

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... TIME AND AMPLITUDE W.R.T THE CLOCK WAVEFORM. I PLL AND SYNCOUT ARE DIGITAL VIDEO OUTPUT SIGNALS THE ONLY RELEVENT OUTPUT TIMING SPECIFICATION 16 FOR I AND SYNCOUT. PLL Figure 10. Analog Output Response vs. CLOCK –7– ADV7150 START OF SCAN LINE (N+1) WHITE LEVEL 90 % FULL-SCALE 50 % TRANSITION 10 % BLACK LEVEL ...

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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7150 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

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... PS0 PS0 PS0 PS0 PS1 PS1 PS1 Connect. REV. A ADV7150 PIN ASSIGNMENTS Pin Mnemonic Number Mnemonic PS1 GND GND GND ...

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... ADV7150 Mnemonic RED ( – GREEN ( – BLUE ( – PS0 . . . PS0 , PS1 . . . PS1 LOADIN LOADOUT PRGCKOUT SCKIN SCKOUT CLOCK, CLOCK BLANK SYNC SYNCOUT D0–D9 CE PIN FUNCTION DESCRIPTION Function Pixel Port (TTL Compatible Inputs): 96 pixel select inputs, with 8 bits each for Red, 8 bits for Green and 8 bits for Blue ...

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... Compensation Pin. A 0.1 F capacitor should be connected between this pin and V Phase Lock Loop Output Current (High Impedance Current Source). This output is used to enable multiple ADV7150s along with ADV7151s to be synchronized together with pixel resolution when using an external PLL. This output is triggered either from the falling edge of SYNC or BLANK as determined by bit CR21 of Command Register 2 ...

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... Pixel Port & Clock Control Circuit of the part operational. ADV7152* ADV7151* Pixel Port (Color Data) • The ADV7150 has 96 color data inputs. The part has four (for • 4:1 multiplexing) 24-bit wide direct color data inputs. These are • • ...

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... CLOCK (see “Pipeline Delay & Onboard Calibra- tion” section). A completely phase independent LOADIN signal can be used with the ADV7150, allowing the CLOCK to occur anywhere during the LOADIN cycle. Alternatively, the LOADOUT signal of the ADV7150 can be used ...

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... OUT and LOADIN (LOADOUT(1) and LOADOUT(2)). LOADIN and Pixel Data must conform to the setup and hold times (t and If, however required that the ADV7150 has a fixed number of pipeline delays (t ), LOADOUT and LOADIN must con- PD form to timing specifications t and -t 10 ures ...

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... N CLOCKS (for 4:1 mode for 2:1 mode for 1:1 mode N = 0). The ADV7150 has onboard calibration circuitry which synchronizes pixel data and LOADIN with the internal ADV7150 clocking signals. Calibra- tion can be performed in two ways: during the devices initializa- tion sequence by toggling two bits of the Mode Register, MR10 followed by MR15 writing a “ ...

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... BLUE BLUE DAC OUT PIXEL PORT MAPPING The pixel data to the ADV7150 is automatically mapped in the parts pixel port as determined by the pixel data mode pro- grammed (Bits CR24–CR27 of Command Register 2). Pixel data in the 24-bit True-Color modes is directly mapped to the 24 color inputs R0–R7, G0–G7 and B0–B7. ...

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... Figure 26. (Note: Data on unused pixel inputs is ignored.) REV. A MICROPROCESSOR (MPU) PORT The ADV7150 supports a standard MPU Interface. All the 256 x 10 functions of the part are controlled via this MPU port. Direct RAM access is gained to the Address Register, Mode Register and all (RED LUT) the Control Registers as well as the Color Palette ...

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... C1 Figure 27. MPU Port and Register Configuration Register Accesses The MPU can write to or read from all of the ADV7150s regis- ters. C0 and C1 determine whether the Mode Register or Ad- dress Register is being accessed. Access to these registers is direct. The Control Registers are accessed indirectly. The Address Register must point to the desired Control Register ...

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... Read GREEN RAM Location Read GREEN RAM Location Read BLUE RAM Location Read BLUE RAM Location (RAM Location Pointed to by Address Register (A7–A0)) Address Register = Address Register + 1 –19– ADV7150 Result DB7–DB0 MR17–MR10 DB7–DB0 A7–A0 DB7–DB0 Control Register DB9– ...

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... The output clocking signals are also set during this reset period. PRGCKOUT = CLOCK/32 LOADOUT = CLOCK/4 The power-on reset is activated when This reset is active for 1 s. The ADV7150 should not be accessed during this reset period. The pixel clock should be applied at power-up. MR19 ...

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... Priority Select Inputs” section. CONTROL REGISTERS The ADV7150 has 9 control registers. To access each register, two write operations must be performed. The first write to the address register specifies which of the 9 registers ac- cessed ...

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... ADV7150 COMMAND REGISTER 2 (CR2) (Address Reg (A7–A0) = 06H) This register contains a number of control bits as shown in the diagram. CR2 is a 10-bit wide register. However, for program- ming purposes, it may be considered as an 8-bit wide register (CR28 and CR29 are both reserved). The diagram shows the various operations under the control of CR2 ...

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... Command Register 3 (CR3) (CR39–CR30) –23– ADV7150 ). As the BLANK control normally enters the PD CR32 CR31 CR30 ) LOADOUT LOADOUT PD · · LOADOUT PD PRGCKOUT FREQUENCY CONTROL ...

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... SYNC LEVEL 0 Decoded on IOG; Pedestal = 0 IRE 265 . SET Reference Input and R An external 1.23 V voltage reference is required to drive the analog outputs of the ADV7150. The reference voltage is con- nected to the V A resistor R and ground. For specified performance, R and V as well as PLL REF 280 . This corresponds to the generation of RS-343A video levels (with SYNC on IOG and Pedestal = 7 ...

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... No SYNC decoded; Pedestal = 0 IRE I Synchronization Output Control PLL This output synchronization signal is used in applications where BLACK necessary to synchronize multiple palette devices (ADV7150 BLANK + ADV7151) to subpixel resolution. Each devices I LEVEL signal is in phase with its analog RGB output signal. If multiple SYNC ...

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... Best performance is obtained with 0.1 F ceramic capacitor decoupling. Each group of V pins on the ADV7150 must have at least one 0.1 F decoupling capacitor to GND. These capacitors should be placed as close as possible to the device. ...

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... Any active termination resistors for the digital inputs should be connected to the regular PCB power plane (V analog power plane. Analog Signal Interconnect The ADV7150 should be located as close as possible to the out- put connectors to minimize noise pick-up and reflections due to impedance mismatch. The video output signals should overlay the ground plane, and not the analog power plane, to maximize the high frequency power supply rejection ...

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... On the other hand, when quantized to 10 bits via the 10-bit RAMs and 10-bit DACs of the ADV7150, all changes on the input 8-bit data are reflected in corresponding changes in the 10-bit data. ...

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... Mode Register MR1. PS0 and PS1 inputs will select one of the preprogrammed devices at any instant when PS0, PS1 matches MR16, MR17, respectively. PS0 and PS1 are multi- plexed similar to the pixel data, thus allowing for subpixel resolu- tion. The diagrams show an example of one ADV7150 operating in ADV7150 R0–R7 G0–G7 ...

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... FFH (Blue Data) to RAM Location (FFH) **These four command lines reset the ADV7150. The pipelines for each of the Red, Creen and Blue pixel inputs are synchronously reset to the Multiplexer’s “A” input. Mode Register bit MR10 is written by a “1” followed by “0” followed by “1.” LOADIN/LOADOUT timing is internally synchronized by writing a “0” ...

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... Data) to RAM Location (FFH) **These four command lines reset the ADV7150 The pipelines for each of the Red, Green and Blue pixel inputs are synchronously reset to the Multiplexer’s “A” in- put. Mode Register bit MR10 is written by a “1” followed by “0” followed by “1.” LOADIN/LOADOUT timing is internally synchronized by writing a “0” followed by a “ ...

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... Bit R7. The following example shows a sequence with the ADV7150 preset to sample the graphics pipeline on a low to high transition of R7. RED ...

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... This provides a highly effi- cient path for the transfer of heat to the package surface. The package configuration also provides an efficient thermal path from the ADV7150 to the Printed Circuit Board via the leads. Heatsinks The maximum silicon junction temperature should be limited to ...

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... ADV7150 0.037 (0.95) 0.026 (0.65) 0.004 (0.10) APPENDIX 8 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). S-160 160-Lead Plastic Power Quad Flatpack 1.239 (31.45) 1.219 (30.95) 0.160 (4.07) 1.107 (28.10) MAX 1.100 (27.90 120 121 4 4 MAX TOP VIEW (PINS DOWN) SEATING PLANE PIN 1 10 160 1 MAX 0.070 (1.77) 0.070 (1.77) 0.026 (0.65) MIN ...

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REV. A ...