adv7150 Analog Devices, Inc., adv7150 Datasheet - Page 22

• Manufacturer Part Number: adv7150
• Description: Cmos 220 Mhz True-color Graphics Triple 10-bit Video Ram-dac
• Manufacturer: Analog Devices, Inc.

ADV7150
COMMAND REGISTER 2 (CR2)
(Address Reg (A7–A0) = 06H)
This register contains a number of control bits as shown in the
diagram. CR2 is a 10-bit wide register. However, for program-
ming purposes, it may be considered as an 8-bit wide register
(CR28 and CR29 are both reserved).
The diagram shows the various operations under the control of
CR2. This register can be read from as well written to. In read
mode, CR28 and CR29 are both returned as zeros.
COMMAND REGISTER 2-BIT DESCRIPTION
R7 Trigger Polarity Control (CR20)
This bit is used when the device is in test/diagnostic mode. It
determines whether the pixel data is latched into the test regis-
ters in the rising or falling edge of R7. (See “Test Diagnostics”
section.)
*THESE BITS ARE READ-
ONLY RESERVED BITS.
A READ CYCLE WILL
RETURN ZEROS "00."
RESERVED*
CR29
CR27
0
1
1
1
0
1
TRUE COLOR/PSEUDO-COLOR MODE CONTROL
CR28
CR26
1
1
1
0
1
0
CR25
1
0
0
0
0
0
CR27
CR24
Command Register 2 (CR2) (CR29–CR20)
1
0
0
0
0
0
CR26
PEDESTAL ENABLE
CR23
0
1
8-BIT PSEUDO COLOR ON R7–R0
8-BIT PSEUDO COLOR ON G7–G0
8-BIT PSEUDO COLOR ON B7–B0
15-BIT TRUE COLOR ON
15-BIT TRUE COLOR ON
24-BIT TRUE COLOR
CONTROL
R7–R3, G7–G3, B7–B3
R7–R0, G6–G0
R7–R0, G7–G0, B7–B0
CR25
0 IRE
7.5 IRE
MODE
–22–
CR24
I
This bit specifies whether the I
BLANK or SYNC.
SYNC Recognition Control (CR22)
This bit specifies whether the video SYNC input is to be
encoded onto the IOG analog output or ignored.
Pedestal Enable Control (CR23)
This bit specifies whether a 0 IRE or a 7.5 IRE blanking pedes-
tal is to be generated on the video outputs.
True-Color/Pseudo-Color Mode Control (CR27–CR24)
These 4 bits specify the various color modes. These include a
24-bit true-color mode, two 15-bit true-color modes and three
8-bit pseudo color modes.
PLL
Trigger Control (CR21)
SYNC RECOGNITION
CR22
CR23
0
1
CONTROL
I
PLL
CR21
IGNORE
DECODE
CR22
TRIGGER CONTROL
0
1
POLARITY CONTROL
CR20
CR21
R7 TRIGGER
SYNC
BLANK
1
0
PLL
output is triggered from
CR20
REV. A